I am trying to add a register slice to an AXI ASIB in my NIC-400 configuration using the uArchitecture Editor in Socrates. The Timing Closure tab gives me the options of "time_closure" and "present" for each AXI channel. What is the difference between these two options?
Never mind, I found the answer in section 9.5.12 of the User Guide.
present = A register slice always exists at this location
time_closure = A register slice "might" exist at this location, meaning you have the ability to add one later by editing a Verilog file instead of going through Socrates to regenerate the RTL.