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error when compiling ClockDiv_XilinxS6.v on Nexys3

Mustapha

Dear All,

My question is very basic : how should I fix this error when compiling ClockDiv_XilinxS6.v on Nexys3 ? how i should change this verilog  code ?   the answer recored 56113 don't provide the needed code just only the technical/schematic solution.

Error : PhysDesignRules:2502 - Issue with pin connections and/or configuration on block:<uClockDiv/uBUFIO2>:<BUFIO2_BUFIO2>.  BUFIO2 has an invalid setting of DIVIDE by 2. This setting is not supported. For more information please see Answer Record 56113.

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    Problem fixed by creating new Ip instead of clockDiv_XlinixS6.V : delete existent uclockdiv. Then create new IP : New source, IP (core generator), name: ClockDiv. Use wizard to create a simple clock div with only input(100MHz) and output (50 MHz)

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    Problem fixed by creating new Ip instead of clockDiv_XlinixS6.V : delete existent uclockdiv. Then create new IP : New source, IP (core generator), name: ClockDiv. Use wizard to create a simple clock div with only input(100MHz) and output (50 MHz)

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