Measuring performance of programs on the FVP

Hi Mohannad,

adding some more detail to Ronan's answer on Fast Models Timing Annotation.

Each of the Fast Models CPU Models has parameters "cpi_mul" and "cpi_div".  By default, Fast Models execute 1 instruction per clock tick, i.e., CPI = 1).  These parameters can be used to modify that.  e.g. to get a CPI of 1.25, you would set cpi_mul=5, cpi_div=4.  (Fast Models doesn't support real numbers as parameters, so to create a fraction you need the two integer parameters).

Caches (and TLB Page Tables, etc) in Fast Model CPUs have a set of parameters to define estimated latency caused by accesses.  By default cache modelling is set OFF in the Fast Model as it won't affect software functionality.  In order for the latency to be applied to accesses cache modelling must be switched on by parameter.  This can be done at the start of simulation or at a pre-defined clock count in the simulation.

The delays on downstream Memory Accesses are not directly supported on the FVP.  These rely on annotating the delay to SystemC/TLM b_transport transactions between the CPU and downstream models.  As the FVP does not use these there is no way of inserting the delay.  Using Fast Models and building the platform from source is required.  You could use the delay annotation on cache miss operations for the outermost cache (the L2 in the Base FVP) that include an estimated delay for a downstream memory access.  Note: although memory is the most usual use of the TA it could be on peripherals, or interconnects, or other components as long as they are using b_transports between the CPU model and the component.

In general, to use the Timing Annotations that are available requires that TA is enabled in the Fast Model.  It is set off by default.  This is done by setting the environment variable "FASTSIM_DISABLE_TA" to 0 before starting the model. 

Hi Mohannad,

adding some more detail to Ronan's answer on Fast Models Timing Annotation.

Each of the Fast Models CPU Models has parameters "cpi_mul" and "cpi_div".  By default, Fast Models execute 1 instruction per clock tick, i.e., CPI = 1).  These parameters can be used to modify that.  e.g. to get a CPI of 1.25, you would set cpi_mul=5, cpi_div=4.  (Fast Models doesn't support real numbers as parameters, so to create a fraction you need the two integer parameters).

Caches (and TLB Page Tables, etc) in Fast Model CPUs have a set of parameters to define estimated latency caused by accesses.  By default cache modelling is set OFF in the Fast Model as it won't affect software functionality.  In order for the latency to be applied to accesses cache modelling must be switched on by parameter.  This can be done at the start of simulation or at a pre-defined clock count in the simulation.

The delays on downstream Memory Accesses are not directly supported on the FVP.  These rely on annotating the delay to SystemC/TLM b_transport transactions between the CPU and downstream models.  As the FVP does not use these there is no way of inserting the delay.  Using Fast Models and building the platform from source is required.  You could use the delay annotation on cache miss operations for the outermost cache (the L2 in the Base FVP) that include an estimated delay for a downstream memory access.  Note: although memory is the most usual use of the TA it could be on peripherals, or interconnects, or other components as long as they are using b_transports between the CPU model and the component.

In general, to use the Timing Annotations that are available requires that TA is enabled in the Fast Model.  It is set off by default.  This is done by setting the environment variable "FASTSIM_DISABLE_TA" to 0 before starting the model. 

Hello Rob,

Thank you very much for the detailed explanation. This will help! I will experiment with this further and will come back to ask if I have any questions. 

Mohannad Ismail