Hello,
I'm workign in a SoC integration of a Cortex-M0 core. I've done my research but I can't seem to find an answer to an, in theory, easy question. Appreciate if someone can point me on the right direction.
We have prototyped the Cortex M0 system MCU into an FPGA using the system design kit. The ROM is modelled in the FPGA as a RAM block, and it can be reprogrammed when in debug mode via the SWD debugger. The program memory can also be "hard" programmed via synthesys.
However, and here is the question, I fail to understand how the "flash download" works. Maybe I am misunderstanding something system-level, but I would think that the SWD debugger should be able to, out of debug mode, to just program the flash, and let the processor start runnign the program. This is what I understand as flash download. In final silicon this would require of some sort of flash algorithm to write to flash, but I would expect this not necessary on FPGA as it is just modelled as a number of registers.
I've had a look at a lot of documents (ARM Debug Interface v5 Architecture Specification (ARM IHI 0031), ARM CoreSight Architecture Specification (ARM IHI 0029)), but they never mention anything related to flash download
What I am missing here?
Thanks
Many thanks Don for your answer I really appreciate it. Actually I was considering using an external memory sd_card/EEPROM with the code inside. Then designing a simple SPI module that has a sole function, on power on, it transfers the code into an sram which is multiplexed with the code ROM to overcome the problem of embedding a FLASH macro. Less SoC design related, but it get things done.