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strobe

there is no strobe for read data bus in AXI, so how the master will acknowledge that which byte lanes carry the valid read data?

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  • The master knows which data bytes it's interested in (since it's the master that requested the write), and so there's no need for the slave to signal which bytes are valid and which bytes aren't.

    By contrast, for a write, the slave has no idea which bytes are intended to be valid and so the master must signal that information.

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  • The master knows which data bytes it's interested in (since it's the master that requested the write), and so there's no need for the slave to signal which bytes are valid and which bytes aren't.

    By contrast, for a write, the slave has no idea which bytes are intended to be valid and so the master must signal that information.

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