I'm working with the obsfucated RTL for Cortex-M3. I have a working design that muxes the 3 AHB-lite buses to 2 AXI3 buses. This design is analogous to the Xilinx designstart design with a code bus and a system bus. The processor correctly boot from the code bus and executes instructions (ITCM disabled). The problem is I see no difference on the AXI bus between normal LDR/STR and LDREX/STREX. I had expected AxLOCK to be set so a monitor can be implemented according to : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGCFAF.html
No matter what I try it appears the STREX instruction fails (returns 1). Even when BRESP is set to 2'b01 after the write. All of this would be fine if it worked properly with the DTCM enabled but those exclusive writes fail as well...
Any ideas on what else to check?
How does the AHB-lite bus handle exclusive access? Maybe something is missing in the translation?
Thanks!
You have two basic methods for sharing a resource (well maybe more, but here are two). One is you use this shared memory location and each user of the shared resource, fights to win control over the memory location. When you win you then talk to the resource directly krogerfeedback