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Instruction and data cache dump from a-53

RCReddy

Hi ARM experts,

                         Before posting , i went through 

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500d/DDI0500D_cortex_a53_r0p2_trm.pdf 

6.7: - Direct access to internal memory

 

c0 0 CDBGDR0 UNK Cache Debug Data Register 0, see Direct access to internal memory
1 CDBGDR1 UNK Cache Debug Data Register 1, see Direct access to internal memory
2 CDBGDR2 UNK Cache Debug Data Register 2, see Direct access to internal memory
3 CDBGDR3 UNK Cache Debug Data Register 3, see Direct access to internal memory
c2 0 CDBGDCT UNK Cache Debug Data Cache Tag Read Operation Register, see Direct access to internal memory
1 CDBGICT UNK Cache Debug Instruction Cache Tag Read Operation Register, see Direct access to internal memory
c4 0 CDBGDCD UNK Cache Debug Cache Debug Data Cache Data Read Operation Register, see Direct access to internal memory
1 CDBGICD UNK Cache Debug Instruction Cache Data Read Operation Register, see Direct access to internal memory
2 CDBGTD UNK Cache Debug TLB Data Read Operation Register, see Direct access to internal memory

Objective: - I want to read entire I-cache and D-cache from Software. 

Statement: -  "The Cortex-A53 processor provides a mechanism to read the internal memory used by the Cache and TLB structures through IMPLEMENTATION-DEFINED system registers".

notes: -  The above statement in the TRM pdf says mechanism to read memory used by Cache. 

questions: - 

[1] I assume that the statement meant Cache memory itself not other memory? 

[2] Is there any example code, as to read the I or D-cache using the registers?

[3] If reading is possible, how to lock I and D-Cache state from further Caching operations and then read it?

Thanks

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