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SRAM for Cortex M0 -- Does It Need to Support Byte write?

Ming

For the SRAM with Cortex M0, does it need to support byte write?

What restrictions do I have with Cortex M0 if the SRAM only support 32-bit write?

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    Yes the SRAM needs to support byte writes. The ARM architecture and the AMBA specification assumes that the memory system allows byte access. All standard tool chains generate code that includes byte-level accesses and standard library code also includes byte-level accesses.

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    Yes the SRAM needs to support byte writes. The ARM architecture and the AMBA specification assumes that the memory system allows byte access. All standard tool chains generate code that includes byte-level accesses and standard library code also includes byte-level accesses.

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