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PL031 verilog generation

nicolan nicolan
Note: This was originally posted on 19th February 2009 at http://forums.arm.com

Pls, I need an answer to a blocking issue  :rolleyes:

I tried to generate a verilog code for PL031 connection matrix 2x3.
Unfortunely generated HSEL signal for each slave doesn't work properly.
In "AxiToAhbWrapper" output verilog file, in fact,  following assign appears:

assign HSEL =1'b1;

and because this block is "copied" for all the master interface inside, then all "HSELx" signals are put high.

What's appens?!

regards
Nicola
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