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Bus Matrix

Felix Varghese
Note: This was originally posted on 28th January 2009 at http://forums.arm.com

What exactly is a bus matrix? I came across the term in ARM cortex M3 specs but couldnt find any proper description. Can someone help?
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  • 0 Arm Employee Badge
    Note: This was originally posted on 31st January 2009 at http://forums.arm.com

    ...And what is the point of this kind of an arrangement?


    The bus-matrix on the Cortex-M3 is a basic arbiter and router, connecting three sources of transactions (load/stores from the core, instruction fetches from the core and debug read/writes from the debug access port) to the M3's four destinations, the instruction and data code busses, the system bus and the NVIC/private-peripheral space.

    In the best case this should allow multiple transactions to be handled simultaneously, e.g. instruction fetch from instruction-code-bus in parallel with data store to system bus; in the worst case it ensures that simultaneous requests from multiple sources to the same destination occur in the correct order based upon the priority assigned to the source.

    hth
    s.
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  • 0 Arm Employee Badge
    Note: This was originally posted on 31st January 2009 at http://forums.arm.com

    ...And what is the point of this kind of an arrangement?


    The bus-matrix on the Cortex-M3 is a basic arbiter and router, connecting three sources of transactions (load/stores from the core, instruction fetches from the core and debug read/writes from the debug access port) to the M3's four destinations, the instruction and data code busses, the system bus and the NVIC/private-peripheral space.

    In the best case this should allow multiple transactions to be handled simultaneously, e.g. instruction fetch from instruction-code-bus in parallel with data store to system bus; in the worst case it ensures that simultaneous requests from multiple sources to the same destination occur in the correct order based upon the priority assigned to the source.

    hth
    s.
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