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AHB frequency

Note: This was originally posted on 6th January 2009 at http://forums.arm.com

Hi Friends,

My doubt is : what is the maximum AHB clock frequency ?

Regards,
P.Vignesh Prabhu

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0 Peter Harris over 12 years ago

Note: This was originally posted on 7th January 2009 at http://forums.arm.com

If you are designing an SoC then all of the usual issues with frequency and bus pipelines come into play here.

You can clock almost any bus very fast, but may need to include more register slices (effectively pipeline stages) to allow a bus transaction to propagate over multiple cycles. The downside is that you have higher latency to access a particular location. There is a tradeoff between bus frequency and latency, as well as other design constraints such as power (slow bus clocks consume much less power).

The bus width of most implementations is also scalable - so you can get a slow clocked bus which is 256-bits wide. Obviously this can carry more data than an 8-bit bus which is clocked 4 times faster. So clock speed isn't everything.

The final aspect for a design which determines the clock speed is the physical process the SoC is manufactured on. A 180nm device on bulk CMOS won't clock as fast as a 45nm device on SOI, and so the achievable clock rate will be capped.

As Sim said, it all depends on the implementation...
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0 Peter Harris over 12 years ago

Note: This was originally posted on 7th January 2009 at http://forums.arm.com

If you are designing an SoC then all of the usual issues with frequency and bus pipelines come into play here.

You can clock almost any bus very fast, but may need to include more register slices (effectively pipeline stages) to allow a bus transaction to propagate over multiple cycles. The downside is that you have higher latency to access a particular location. There is a tradeoff between bus frequency and latency, as well as other design constraints such as power (slow bus clocks consume much less power).

The bus width of most implementations is also scalable - so you can get a slow clocked bus which is 256-bits wide. Obviously this can carry more data than an 8-bit bus which is clocked 4 times faster. So clock speed isn't everything.

The final aspect for a design which determines the clock speed is the physical process the SoC is manufactured on. A 180nm device on bulk CMOS won't clock as fast as a 45nm device on SOI, and so the achievable clock rate will be capped.

As Sim said, it all depends on the implementation...
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