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AHB Bufferable/Non-bufferable write

Hariprem Arora
Note: This was originally posted on 12th September 2008 at http://forums.arm.com

Hi,

Please clarify the following issue related to AHB write:

If HPROT[2] = 1, AHB write is bufferable and we need to provide OKAY response as soon as the AHB slave interface receives data without caring that the data is actually written into the memory or not.

if HPROT[2] = 0, AHB write is non-bufferable, AHB slave interface needs to provide response to the master only when the data is actually written into the memory.

The issue is that if we see this non-bufferable transaction, the state of HRESP will by default be OKAY (HREADY is HIGH to accept the next data) and it means that we are providing the response in advance for non-bufferable write.

Please clarify how to distinguish between the two transactions.
If possible, please provide waveforms for INCR undefined length & non-bufferable write
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  • 0
    Note: This was originally posted on 15th September 2008 at http://forums.arm.com

    Hi Hari,

    If you have a module that registers a transfer between the master and slave, and you do want the real transfer response from the destination slave, yes, you will need to add at least one wait state per data transfer to allow this registering component time to sample the real response and then drive it back to the master.

    This will affect throughput, so you need to look at why you are putting in this registering component - is it to another bus protocol, or is it to break a long timing path.

    Can you restructure the architecture to avoid this registering component, or design the destination slave so that it will always give back an OKAY response that can be safely handled as a buffered write ?

    Sorry but if you want to buffer writes AND get the real slave response, you will need wait states that will reduce throughput.

    JD
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  • 0
    Note: This was originally posted on 15th September 2008 at http://forums.arm.com

    Hi Hari,

    If you have a module that registers a transfer between the master and slave, and you do want the real transfer response from the destination slave, yes, you will need to add at least one wait state per data transfer to allow this registering component time to sample the real response and then drive it back to the master.

    This will affect throughput, so you need to look at why you are putting in this registering component - is it to another bus protocol, or is it to break a long timing path.

    Can you restructure the architecture to avoid this registering component, or design the destination slave so that it will always give back an OKAY response that can be safely handled as a buffered write ?

    Sorry but if you want to buffer writes AND get the real slave response, you will need wait states that will reduce throughput.

    JD
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