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AHB Bufferable/Non-bufferable write

Hariprem Arora
Note: This was originally posted on 12th September 2008 at http://forums.arm.com

Hi,

Please clarify the following issue related to AHB write:

If HPROT[2] = 1, AHB write is bufferable and we need to provide OKAY response as soon as the AHB slave interface receives data without caring that the data is actually written into the memory or not.

if HPROT[2] = 0, AHB write is non-bufferable, AHB slave interface needs to provide response to the master only when the data is actually written into the memory.

The issue is that if we see this non-bufferable transaction, the state of HRESP will by default be OKAY (HREADY is HIGH to accept the next data) and it means that we are providing the response in advance for non-bufferable write.

Please clarify how to distinguish between the two transactions.
If possible, please provide waveforms for INCR undefined length & non-bufferable write
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  • 0 Arm Employee Badge
    Note: This was originally posted on 12th September 2008 at http://forums.arm.com

    Hi Hari,

    > If HPROT[2] = 1, AHB write is bufferable and we need to
    > provide OKAY response as soon as the AHB slave interface
    > receives data without caring that the data is actually written
    > into the memory or not.

    First thing is that you do not need to provide a response from any intermediate module (rather than the destination slave), this is only an option for you to consider to speed up the transfers for bufferable writes.

    Next thing is that you do not need to provide an OKAY response. If your intermediate component decides that a transfer is not allowed, it could give an ERROR response.

    > if HPROT[2] = 0, AHB write is non-bufferable, AHB slave
    > interface needs to provide response to the master only when
    > the data is actually written into the memory.
    >
    > The issue is that if we see this non-bufferable transaction, the
    > state of HRESP will by default be OKAY (HREADY is HIGH to
    > accept the next data) and it means that we are providing the
    > response in advance for non-bufferable write.

    Yes, that is the risk with providing the early response, if the destination slave decides on a different response you cannot change anything.

    > Please clarify how to distinguish between the two transactions.

    Well you already know how to distinguish between them, that is what the HPROT[2] signal is for.

    > If possible, please provide waveforms for INCR undefined length &
    > non-bufferable write

    There is nothing special here that I would think needs extra waveforms. If the burst sequence is non-bufferable, and you are going via some interim buffering module, you will just see additional wait states for each access while it completes through to the destination device and a real response is returned to the originating master.

    JD
Reply
  • 0 Arm Employee Badge
    Note: This was originally posted on 12th September 2008 at http://forums.arm.com

    Hi Hari,

    > If HPROT[2] = 1, AHB write is bufferable and we need to
    > provide OKAY response as soon as the AHB slave interface
    > receives data without caring that the data is actually written
    > into the memory or not.

    First thing is that you do not need to provide a response from any intermediate module (rather than the destination slave), this is only an option for you to consider to speed up the transfers for bufferable writes.

    Next thing is that you do not need to provide an OKAY response. If your intermediate component decides that a transfer is not allowed, it could give an ERROR response.

    > if HPROT[2] = 0, AHB write is non-bufferable, AHB slave
    > interface needs to provide response to the master only when
    > the data is actually written into the memory.
    >
    > The issue is that if we see this non-bufferable transaction, the
    > state of HRESP will by default be OKAY (HREADY is HIGH to
    > accept the next data) and it means that we are providing the
    > response in advance for non-bufferable write.

    Yes, that is the risk with providing the early response, if the destination slave decides on a different response you cannot change anything.

    > Please clarify how to distinguish between the two transactions.

    Well you already know how to distinguish between them, that is what the HPROT[2] signal is for.

    > If possible, please provide waveforms for INCR undefined length &
    > non-bufferable write

    There is nothing special here that I would think needs extra waveforms. If the burst sequence is non-bufferable, and you are going via some interim buffering module, you will just see additional wait states for each access while it completes through to the destination device and a real response is returned to the originating master.

    JD
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