Arm Community
Site
Search
User
Site
Search
User
Groups
Education Hub
Distinguished Ambassadors
Open Source Software and Platforms
Research Collaboration and Enablement
Forums
AI and ML forum
Architectures and Processors forum
Arm Development Platforms forum
Arm Development Studio forum
Arm Virtual Hardware forum
Automotive forum
Compilers and Libraries forum
Graphics, Gaming, and VR forum
High Performance Computing (HPC) forum
Infrastructure Solutions forum
Internet of Things (IoT) forum
Keil forum
Morello forum
Operating Systems forum
SoC Design and Simulation forum
SystemReady Forum
Blogs
AI and ML blog
Announcements
Architectures and Processors blog
Automotive blog
Graphics, Gaming, and VR blog
High Performance Computing (HPC) blog
Infrastructure Solutions blog
Internet of Things (IoT) blog
Operating Systems blog
SoC Design and Simulation blog
Tools, Software and IDEs blog
Support
Arm Support Services
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Support forums
SoC Design and Simulation forum
AHB Bufferable/Non-bufferable write
Jump...
Cancel
State
Not Answered
Locked
Locked
Replies
8 replies
Subscribers
88 subscribers
Views
15407 views
Users
0 members are here
AHB.AMBA
Bus Architecture
Options
Share
More actions
Cancel
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion
AHB Bufferable/Non-bufferable write
Hariprem Arora
over 11 years ago
Note: This was originally posted on 12th September 2008 at
http://forums.arm.com
Hi,
Please clarify the following issue related to AHB write:
If HPROT[2] = 1, AHB write is bufferable and we need to provide OKAY response as soon as the AHB slave interface receives data without caring that the data is actually written into the memory or not.
if HPROT[2] = 0, AHB write is non-bufferable, AHB slave interface needs to provide response to the master only when the data is actually written into the memory.
The issue is that if we see this non-bufferable transaction, the state of HRESP will by default be OKAY (HREADY is HIGH to accept the next data) and it means that we are providing the response in advance for non-bufferable write.
Please clarify how to distinguish between the two transactions.
If possible, please provide waveforms for INCR undefined length & non-bufferable write
Parents
0
Hariprem Arora
over 11 years ago
Note: This was originally posted on 16th September 2008 at
http://forums.arm.com
Hi JD,
Its clear that we need to insert wait states if we want to have destination slave response.
From here we have following approaches for non-bufferable writes:
Approach 1 :
i) Do specified length transfers with last data transfer done by inserting wait state so that real response can be taken for whole burst.
ii) Do unspecified length transfers with each data transfer done by inserting wait state because slave doesn't know when the last data transfer will occur.
Approach 2 :
Remove the unspecified length transfer feature so that it doesn't effect throughput (as wait state is inserted for each data transfer in a burst to get real response).
Please suggest if the above approaches feasible.
Hari
Cancel
Up
0
Down
Cancel
Reply
0
Hariprem Arora
over 11 years ago
Note: This was originally posted on 16th September 2008 at
http://forums.arm.com
Hi JD,
Its clear that we need to insert wait states if we want to have destination slave response.
From here we have following approaches for non-bufferable writes:
Approach 1 :
i) Do specified length transfers with last data transfer done by inserting wait state so that real response can be taken for whole burst.
ii) Do unspecified length transfers with each data transfer done by inserting wait state because slave doesn't know when the last data transfer will occur.
Approach 2 :
Remove the unspecified length transfer feature so that it doesn't effect throughput (as wait state is inserted for each data transfer in a burst to get real response).
Please suggest if the above approaches feasible.
Hari
Cancel
Up
0
Down
Cancel
Children
No data