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Confusion over AMBA AHB hsize[] signal definition

Note: This was originally posted on 26th February 2008 at http://forums.arm.com

After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface. If an AHB bus is implemented using 32 bit write and read data buses, I would think this would imply that hsize[2] is essentially unused and always '0' since data transfer width on this bus can only be a byte, half word, or word. Yet, I see interface signal specifications on various 32 bit bus AHB designs where hsize[2] seems to be used and is not optimized out even after synthesis?? My understanding of HSIZE[] and HBURST[] signals is that HBURST[] determines the number of data transfer beats on the bus for a burst transaction whereas HSIZE determines the data width of each transfer. The spec. seems to be vague on this with no examples.

dave mc