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Confusion over AMBA AHB hsize[] signal definition

davemac2 davemac2
Note: This was originally posted on 26th February 2008 at http://forums.arm.com

After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface.  If an AHB bus is implemented using 32 bit write and read data buses, I would think this would imply that hsize[2] is essentially unused and always '0' since data transfer width on this bus can only be a byte, half word, or word.  Yet, I see interface signal specifications on various 32 bit bus AHB designs where hsize[2] seems to be used and is not optimized out even after synthesis??  My understanding of HSIZE[] and HBURST[] signals is that HBURST[] determines the number of data transfer beats on the bus for a burst transaction whereas HSIZE determines the data width of each transfer.  The spec. seems to be vague on this with no examples.

dave mc
  • 0
    Note: This was originally posted on 22nd July 2008 at http://forums.arm.com

    Yes...
    If you are having system with 32 bit data bus or 64 bit data bus....
    you can remove HSIZE[2]...
    sysnthesis tools of nowadays will also remove it automatically...
  • 0
    Note: This was originally posted on 21st July 2008 at http://forums.arm.com

    After reading the AMBA AHB spec rev 2, I am still confused over the relationship of the HSIZE[2:0] signal and the implemented bus width on an interface.  If an AHB bus is implemented using 32 bit write and read data buses, I would think this would imply that hsize[2] is essentially unused and always '0' since data transfer width on this bus can only be a byte, half word, or word.  Yet, I see interface signal specifications on various 32 bit bus AHB designs where hsize[2] seems to be used and is not optimized out even after synthesis??  My understanding of HSIZE[] and HBURST[] signals is that HBURST[] determines the number of data transfer beats on the bus for a burst transaction whereas HSIZE determines the data width of each transfer.  The spec. seems to be vague on this with no examples.

    dave mc


    Hi,
    Amba AHB supports upto 1024 bus widths(in practical at a max of 256).Therefore Hsize[2:0] is defined.
    If ur using 128 bit data bus,the HSIZE[2] will be "100".
    If ur using configuarable data bus widths of 32,64 or 128 then HSIZE[1:0] will not be sufficient.!!!!!!!!!!!!!!!!
  • 0
    Note: This was originally posted on 28th February 2008 at http://forums.arm.com

    Hi Dave Mc,

    You are correct that HSIZE[2] would never change if your data bus is 32 bits wide as masters cannot issue transfers wider than their natural bus width.

    HSIZE will still be described in specifications for such a master as 3 bits wide because HSIZE is defined as 3 bits, and I'm sure if I designed a master with only 2 bits for HSIZE, the first question I would get would be "What is HSIZE[2] driven to ?".

    As for why the extra unused bit is not optimised out during synthesis, I guess that comes down to the synthesis tools. You wouldn't optimise it out at component level because the signal appears on the bus interface, but I guess some intelligence from the synthesis tool "might" be able to remove the unused net at a system level.

    And your understanding of the meanings of the HSIZE and HBURST signals looks fine to me, so maybe the spec did explain enough after all :(

    JD.
  • 0
    Note: This was originally posted on 21st July 2008 at http://forums.arm.com

    Hemamth,

    Just to correct your reply, if you are using data bus widths of up to 32 (3'b010) or 64 bits (3'b011) wide then HSIZE[1:0] would be sufficient, so it is only once you go above that level when the HSIZE[2] bit would be required.

    JD