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AXI Read/Write ordering

Randy Pascarella
Note: This was originally posted on 24th October 2007 at http://forums.arm.com

Hello,
   Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them.  It then says that if a RAW dependency exists, the master must wait for the write to fully complete before issuing the read.  If the write is bufferable, the response comes from the AXI target.  If that target is a bridge to another I/O or host protocol, what should the master expect?  I can think of two answers:

a) Master must punctuate a series of bufferable writes with a non-bufferable write (same AWID) to ensure that all write data has reached the final destination.  Non-bufferable write response receipt indicates the read may then be issued.

-or-

b) Master assumes that the target device will maintain RAW ordering beyond AXI.  Master issues a series of bufferable writes (same AWID) and issues the read once the last bufferable write response has been received.  Writes are buffered in the target bridge and the read then causes the target bridge to flush out the bufferable writes before issuing the read on the other side.

The RAW dependency can be either an address collision with a previous write, or perhaps a previous write has side-effects that may affect the read, such as opening up a window of memory space for the read to access.  Is the type of RAW dependency expected to change the master's choice of bufferable vs. non-bufferable write?

Any comments?  What does AXI require here?

Thanks!
Randy
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