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AXI write strobes

jameskim jameskim
Note: This was originally posted on 21st February 2007 at http://forums.arm.com

the AXI spec says:

10.1 About unaligned transfers
[...]
For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be accessed do not align with the natural data width boundary. For example, a 32-bit (four-byte) data packet that starts at a byte address of 0x1002 is not aligned to a 32-bit boundary.


and then shows some examples of bursts with unaligned first bytes.

i also see references to disabling all strobes on any beat of a burst write.

but, what about unaligned ending bytes?  for example, a burst of 1kB starting at address 0x1 would have both an unaligned starting and ending byte.  is this allowed?

do the bytes of a burst have to be contiguous?  could the writes strobes have holes in them, for example, 0x5, 0xa, 0x9, etc.?

also, i was wondering what AXI masters ARM has that makes use of this feature?  do ARM processors ever generate unaligned bursts for instruction or data accesses, or is it only the DMA controller that issues unaligned bursts?  and in what scenario would a master disable all the strobes after starting a burst write (something like interrupting a dirty line castout?)?

thanks!
james
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  • 0
    Note: This was originally posted on 28th February 2007 at http://forums.arm.com

    > do the bytes of a burst have to be contiguous?  could the writes
    >  strobes have holes in them, for example, 0x5, 0xa, 0x9, etc.?

    The write strobes can change for each transfer of a burst, so you could see the above sequence.

    > also, i was wondering what AXI masters ARM has that makes
    > use of this feature?

    I am not aware of any current ARM masters that use the WSTRBs to indicate sparse transfers, but maybe someone else will know more about specific ARM master designs.


    I know that, at least, ARM11-MPCore processeur and L220 Level 2 cache controller use sparse strobes. This is due to the fact that they use a merging write buffer. If the application writes several bytes at address 0x0, 0x3, 0x4, the write buffer will be drained using a 64-bit transfer, and strobes will be 0b00011001 and the AXI slave must only update the bytes that are enabled.
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  • 0
    Note: This was originally posted on 28th February 2007 at http://forums.arm.com

    > do the bytes of a burst have to be contiguous?  could the writes
    >  strobes have holes in them, for example, 0x5, 0xa, 0x9, etc.?

    The write strobes can change for each transfer of a burst, so you could see the above sequence.

    > also, i was wondering what AXI masters ARM has that makes
    > use of this feature?

    I am not aware of any current ARM masters that use the WSTRBs to indicate sparse transfers, but maybe someone else will know more about specific ARM master designs.


    I know that, at least, ARM11-MPCore processeur and L220 Level 2 cache controller use sparse strobes. This is due to the fact that they use a merging write buffer. If the application writes several bytes at address 0x0, 0x3, 0x4, the write buffer will be drained using a 64-bit transfer, and strobes will be 0b00011001 and the AXI slave must only update the bytes that are enabled.
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