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AMBA AXI Write response

Sai Krishna
I am just going through the specs of AMBA AXI.
I've few questions.It will be great if anybody clarify
1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in a Read burst ?
2) How to terminate A read/write burst ? Specification says we can not stop bursts intermittantly.
         i) Can A master can give WLAST in middle of a burst transfer ?
         ii) in the same way if slave assersts RLAST before the completion of a busrt read?
If WLAST and RLAST can not do the above cases, then what is the special use of WLAST and RLAST because we are getting individual beat responses anyway?
3) Whats the exact use of Exclusive Read and Write Pair transaction? Where exactly these will be used?

Thanks in advance..
Regards,
Sai Krishna
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  • 0 Arm Employee Badge
    Note: This was originally posted on 30th January 2007 at http://forums.arm.com

    Hi Sai,

    > 3) Is there a possibility that A Read transaction can complete in One Cycle ?

    No.

    It would take a minumum of 1 clock cycle to pass the address from the master to the slave (assumes ARREADY was high when ARVALID was asserted), and then a minimum of 1 clock cycle to pass the data from the slave to the master (assumes RREADY was high when RVALID was asserted).


    >Section 3.1.4 on 3.4 says that "A default ARREADY value of LOW is possible but not recommended, because it implies that the transfer takes at least two cycles, one to assert ARVALID and another to assert ARREADY"

    Yes.

    If ARREADY is initially low when an address is signaled on ARVALID, it will take one clock cycle for the slave to sample this ARVALID and then assert ARREADY (if it can accept the address), and the address handshake then completes on the next clock rising edge (when both ARREADY and ARVALID are high). So 2 clock cycles just to pass the address from master to slave if ARREADY defaults to LOW.

    It would then take at least a further clock cycle before the read data could be returned to the master.

    Colin.
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  • 0 Arm Employee Badge
    Note: This was originally posted on 30th January 2007 at http://forums.arm.com

    Hi Sai,

    > 3) Is there a possibility that A Read transaction can complete in One Cycle ?

    No.

    It would take a minumum of 1 clock cycle to pass the address from the master to the slave (assumes ARREADY was high when ARVALID was asserted), and then a minimum of 1 clock cycle to pass the data from the slave to the master (assumes RREADY was high when RVALID was asserted).


    >Section 3.1.4 on 3.4 says that "A default ARREADY value of LOW is possible but not recommended, because it implies that the transfer takes at least two cycles, one to assert ARVALID and another to assert ARREADY"

    Yes.

    If ARREADY is initially low when an address is signaled on ARVALID, it will take one clock cycle for the slave to sample this ARVALID and then assert ARREADY (if it can accept the address), and the address handshake then completes on the next clock rising edge (when both ARREADY and ARVALID are high). So 2 clock cycles just to pass the address from master to slave if ARREADY defaults to LOW.

    It would then take at least a further clock cycle before the read data could be returned to the master.

    Colin.
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