Hi,
I have one AXI module. from upper side master is doing transaction W/R. for master data bus width is 256bits. transaction comes into module and module split that into 2.> bcoz lower side are two 128 bits databus width slaves. upperbits of data bus WDATA[255:128] goes to slave 1 and lowerbits of data bus WDATA[127:0] goes to slave 2. same for WSTRB[32:16] connected to slave 1 & WSTRB[15:0] connected to slave 2.But in my unit level testing there are 3 protocol checkers. 1 for master and 2 for slave 1& 2. When master initiates the transaction it does not throw any error. but for slave it is throwing error : Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size and beat number. Question: how should wstrb & awaddr & awsize & awlen & awburst work for slave 1 and slave 2. as they are half the data bus width.
Can you list what the original 256-bit transaction and split 128-bit transactions appear as so that we can perhaps comment on what the protocol violation is ?
Please include AWADDR, AWSIZE and AWLEN for each AW channel transfer, and then the WSTRB values for each data transfer in the write transaction.
Does the protocol violation get flagged for EVERY 128-bit transfer, so just one ?
Just thinking about this further, I don't think you can easily do this.
The 256-bit AWADDR value gives the 256-bit start address, and this increments by the AWSIZE value for each transfer in the transaction.
If you try to split these 256 bit transfers acrosss 2 128-bit slaves, with each taking one half of the data bus, each 128-bit slave won't see legal AXI transactions.
As an example the 256-bit start address will usually be correct for the 128-bit slave seeing WDATA[127:0], but you would need to supply a modified AWADDR value to the 128-bit slave seeing WDATA[255:128], the modification being incrementing the start address by 16 bytes so that you are addressing the upper half of the 256-bit path. (I say usually because the start address could be unaligned, which just causes more complexity).
Then for each subsequent transfer in the 256-bit transaction, the downstream 128-bit slaves cannot just increment their own start addresses by their local AWSIZE values (presumably showing 128-bit transfers) because the 128-bit incremented data was what the 256-bit master wrote out on the other half of the 256-bit data bus.
I guess you could drive the 128-bit bus AWLEN values to signal double the original burst length, and then each 2nd transfer on the 128-bit bus has to have WSTRB=16'b0 to signal that no data is being written as that addressed data actually went to the other 128-bit slave.
But I'm guessing a lot here. I just don't see how this can easily work.
As an example, if the 256-bit master does a 4-beat burst to start address 0x0, with the numbers in the data column representing 128-bit data values...
address data
0x00 2 1
0x20 4 3
0x40 6 5
0x60 8 7
...what do you want stored in the 128-bit slaves ?
slave on wdata[127:0] slave on wdata[255:128]
address data address data
0x00 1 0x00
0x10 0x10 2
0x20 3 0x20
0x30 0x30 4
0x40 5 0x40
0x50 0x50 6
0x60 7 0x60
0x70 0x70 8
or did you want the 1 3 5 7 data to be stored in 0x00 0x10, 0x20 and 0x30, and 2 4 6 8 data in the same addresses in the other slave ?
Whatever you want, you need to make sure that the AWADDR, AWLEN and AWSIZE values supplied to each slave give you the start addresses and address increments you want.