According to spec IHI0022D_amba_axi_protocol_spec section A2.1 page number: A2-28
"All signals are sampled on the rising edge of the global clock "
Q) Should RESET_N also be sampled on the rising edge only?
Section A3.1.2, says
"The AXI protocol uses a single active LOW reset signal, ARESETn. The reset signal can be asserted asynchronously, but de-assertion must be synchronous with a rising edge of ACLK.
During reset the following interface requirements apply:• a master interface must drive ARVALID, AWVALID, and WVALID LOW
• a slave interface must drive RVALID and BVALID LOW
"
Q) How a design should implement with respect to reset. ( Should it implement Asynchronous reset)?
Only xVALID signals need driving to LOW during reset, all other signals can take any values as channel payload signals are considered undefined when the channel's xVALID signal is LOW.
There isn't any recommendation of what other signals are driven to during reset, but I would at least select valid values for them to take (for example AxBURST=2'b11 is a reserved combination, so I would not use that as a reset value) until such times as a transfer is required.