AHB protocol

It means that there is no cycle lost when changing between bus masters.

Have a look at figure 3-17 in the original AMBA 2 AHB specification (ARM IHI 0011A) where it shows "Data bus ownership".

In cycle T4 master #1 is driving HTRANS, HADDR, etc., and then in cycle T4 it is master #2 driving the address phase control signals. Similarly for the HWDATA data phase signals master #1 is driving in cycle T6 and master #2 in T7. So no "lost" cycles when changing between masters. 

However if you are new to the AHB protocol, unless you need multi-master support on a single AHB, it might be simpler to look at the AHB-lite protocol where there is only 1 master driving the bus, and where you would use a bus interconnect or BusMatrix to connect together multiple AHB-lite masters and slaves.

It means that there is no cycle lost when changing between bus masters.

Have a look at figure 3-17 in the original AMBA 2 AHB specification (ARM IHI 0011A) where it shows "Data bus ownership".

In cycle T4 master #1 is driving HTRANS, HADDR, etc., and then in cycle T4 it is master #2 driving the address phase control signals. Similarly for the HWDATA data phase signals master #1 is driving in cycle T6 and master #2 in T7. So no "lost" cycles when changing between masters. 

However if you are new to the AHB protocol, unless you need multi-master support on a single AHB, it might be simpler to look at the AHB-lite protocol where there is only 1 master driving the bus, and where you would use a bus interconnect or BusMatrix to connect together multiple AHB-lite masters and slaves.