Hi,
I need a clarification on PENABLE with respect to PREADY. 1) Can pready remain high for more than one cycle? 2) Does PENABLE from the master has to look for PREADY going low to deassert or it should go low the cycle next to the assertion of PREADY?
This might be very basic query, please pardon me as its the first time i'm developing a APB master and slave.
Thanks Nitin
1) yes, PREADY can remain high for multiple cycles.
When not in the "access" phase of a transfer, PREADY is undefined, so could be driven high.
PREADY high could be the default value of this signal, as it only needs to be driven low during the "access" phase of a transfer in which the peripheral wants to add wait states.
2) PENABLE will go low as soon as PREADY is sampled high on a PCLK rising edge. This indicates the end of that APB transfer.
All of the diagrams in the APB specification will show PENABLE go low when PREADY is sampled high on PCLK rising.
So the master asserts PENABLE to start the "access" phase of the transfer, and then each subsequent PCLK rising edge it will check PREADY to see when the "access" phase is ending, at which point it will then de-assert PENABLE.