What is the size of AWID and ARIDs? On what basis size is determined? How the AxIDs are generated?
The width of the AxID outputs of a master will depend on how many different ID values the master wants to use.
Different ID values would usually indicate different processing threads which can operate independently of each other. So a simple single thread AXI master wouldn't have any AxID outputs because all transfers have to complete in the order they were issued, whereas a multi-core AXI master could have many concurrent threads, each then with a number of different ID values to signal which thread the transfer relates to.