I want to know what happens in these scenarios :1) Assume Master1 (M1) is doing locked access, if locked access fails before M1 does unlocking transaction what is the response to the M1? 2) Assume M1 is doing locked transaction, if other Master2 (M2) tries to access the locked interconnect then what is the response to M2?3) If multiple Masters tries to do locked transactions at the same time, which master will get the access?
Regards,Vasu P
1) until M1 signals an unlocking access, the path from M1 to the destination slave remains in a locked state. However an unlocking transfer is simply one with AxLOCK set to 0, so the next transfer M1 performs after the failed locked access will be the unlocking transfer (assuming it doesn't immediately reattempt the failed locked access).
2) If M2 tries to access the same slave locked by M1, or any part of the interconnect internal paths that are locked by M1's access, the M2 access will be stalled until M1 completes its locked transfers.
3) when multiple masters attempts to access the same slave, the interconnect arbitration logic will decide which master's access is passed through and which is stalled. The same is true of locked accesses, the interconnect arbitration logic will decide which access gets through and which is stalled.
In the answer 3 you mentioned arbitration logic
But in axi3.0 there is no concept of priority right and how it can process one by one?can you please explain
If you have 2 AXI masters trying to access one slave, how do you decide which one to get access, and which one to stall ?
Somewhere your "interconnect" logic has to decide which master to select, so that one is given "priority".
"Priority" isn't something signalled by the master (in AXI3), it is something decided by the interconnect, so either master A always is treated as higher priority than master B, or each master is given equal number of cycles access to the slave, or perhaps you can come up with some other scheme to define which master the interconnect selects. But whatever that scheme is, that master given access is being treated as higher priority than the other.
In AXI4 we do now have AxQOS signals that allow each master to indicate the perceived priority of their access so that the interconnect logic can try to make an informed decision as to which master to give priority to.