Hi,
I am developing a RTL code for AHB lite - AXI bridge. I want to understand what are the possible error scenarios in AHB?
1.I can think of invalid address as the only case. Is there any other scenario?
2. I am performing a INCR4 transfer on AHB side. Will I get error response for each transfer or single error response for entire transfer. Can anyone help me with the timing diagram/waveform for the same?
Thanks,
Vijey
1. possible AHB error scenarios, anything the slave isn't happy with - so examples could be only supporting some width transfers, not supporting unprivileged accesses, only supporting read accesses, only supporting opcode fetches, and so on.
2. as far as error responses from the AXI side of your bridge, you get a response for each read data transfer on the AXI protocol, but only one response after the end of a write burst, so how you decide to handle the AHB write burst conversion will determine when you receive AXI write responses.
There wouldn't be any point supplying you with waveforms of how such a burst transfer "COULD" be performed across a bridge as that would be for a specific bridge design implementation, so these are something you would need to decide what your bridge will do.
Sorry to be vague there but there are a number of different ways to perform this conversion, and this isn't something mandated by any of the separate AMBA protocol documents, so detailing one specific solution would just mean you are copying someone else's design. Better that you come up with your own solution to meet the demands of your application.