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armv8 - Aarch32 & Aarch64 binaries within a process

Hello Experts,

Reading armv8 documentation, I understand that switching between execution states require a change of exception levels. I would like to know if I can mix Aarch32 and Aarch64 userspace binaries within a process in the following manner:

1. User space Aarch32 binary (EL0) invokes sys call.

2. Kernel (EL1, Aarch64 code) sets up EL0 stack for Aarch64 and return to a specific address that falls in a Aarch64 shared library. (EL0 LR is set to a different return address)

This of course assumes that the sys call is a new implementation in the kernel that also takes care of Aarch64 ABI before returning to userspace. If this isn't feasible, are there other ways we can get 32-bit and 64-bit binaries within the same process to work atop 64-bit kernel? 

Thanks for reading.

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  • Hi Ben,

    Thanks for your response. This matches what I read as well.

    To help me understand this better, would you please point out which step below will fail:

    1. A32 user space code (Processor mode = Aarch32) invokes sys call to jump to kernel.

    2. Kernel sets SPSR_EL1 mode (M[4] bit) to Aarch64 and ELR_EL1 to point to userspace A64 code (64-bit binary already mapped in the process address space).

    3. Kernel sets SP_EL0 to a newly allocated stack area.

    4. Invoke ERET from kernel.

    Won't this take us back to EL0 (userspace) with the processor in Aarch64 mode capable of executing A64 instructions? I am ignoring ABI details here.

    Again, thanks a lot for looking at this.

Reply
  • Hi Ben,

    Thanks for your response. This matches what I read as well.

    To help me understand this better, would you please point out which step below will fail:

    1. A32 user space code (Processor mode = Aarch32) invokes sys call to jump to kernel.

    2. Kernel sets SPSR_EL1 mode (M[4] bit) to Aarch64 and ELR_EL1 to point to userspace A64 code (64-bit binary already mapped in the process address space).

    3. Kernel sets SP_EL0 to a newly allocated stack area.

    4. Invoke ERET from kernel.

    Won't this take us back to EL0 (userspace) with the processor in Aarch64 mode capable of executing A64 instructions? I am ignoring ABI details here.

    Again, thanks a lot for looking at this.

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