On Intel-based server I can get the SMI cound by reading at the appropriate offset in /dev/cpu/%u/msrOn AMD-based server I can get it from the appropriate performance counterWhat do I do on ARM processors for the same functionality, or are SMIs not a part of the ARM ecosystem?
The reason for asking is that on x86 processors, SMIs interrupt processing from the O.S.'s perspective, and I need to be able to monitor these events.
A bit of background can be found at https://wiki.linuxfoundation.org/realtime/documentation/howto/debugging/smi-latency/smi
While Arm v8+ machines don't have SMI. They do have exceptions/interrupts that can be routed to EL3, where generally you will find Trusted Firmware A. But AFAIK there isn't a standard way to retrieve the number of times an interrupt/exception has fired to EL3. Really, for what I think your doing it should be tracked per core in the system as well, because unlike SMM mode which acts to stop the entire machine an EL3 interrupt will generally only consume a single core during processing. So it is a far less intrusive operation. Much of this is going to be platform dependent with some platforms never doing anything in EL3/etc while some platforms will be doing a lot more heavyweight RAS/sEL0/etc processing. So, check to see if your platform's TFA is public, look at this document TFA interrupt-framework-design. Then you might be able to add a field to intr_type_descs to count the number of times an interrupt has fired from here. Then add a SMCC call/etc to retrieve the values.
Another idea might be to look at the TFA PMU support and an an appropriate counter supported by your platform.