On Intel-based server I can get the SMI cound by reading at the appropriate offset in /dev/cpu/%u/msrOn AMD-based server I can get it from the appropriate performance counterWhat do I do on ARM processors for the same functionality, or are SMIs not a part of the ARM ecosystem?
The reason for asking is that on x86 processors, SMIs interrupt processing from the O.S.'s perspective, and I need to be able to monitor these events.
A bit of background can be found at https://wiki.linuxfoundation.org/realtime/documentation/howto/debugging/smi-latency/smi
I don't know the detail, but... As your link says SMI & SMM are x86 specific. For Arm there are different systems.
This old StackExchange answer may shed some light, as might searching for Secure Monitor on developer.arm.com and also learning about TrustZone etc. Your answer is likely to need more detail about the generation & type of processor (A/M/R series, v7/v8/v9?), and what additional features are added, including by the actual silicon vendor, not just Arm.