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Unsupported Exclusive or Atomic access exception

John K

Hi,

I am receiving an Unsupported Exclusive or Atomic access exception when dereferencing a capability. The ESR value is: 96000035. The same code works fine on bare metal, but under a hypervisor (bhyve) it fails with this exception.

My question is: what does this exception actually mean?

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    The register specification of ESR_ELx can be found in the Arm ARMv8-A (see the link below).

    developer.arm.com/.../

    For example, ESL_EL1 can be found in D19.2.37 ESR_EL1, Exception Syndrome Register (EL1) of the Arm ARMv8-A (J.a) above.

    Since EC (bits [31:26]) is showing 0b100101 in your case, it means:

    EC == 0b100101
    Data Abort exception taken without a change in Exception level.
    Used for MMU faults generated by data accesses, alignment faults other than those
    caused by Stack Pointer misalignment, and synchronous External aborts, including
    synchronous parity or ECC errors. Not used for debug-related exceptions.

    And, DFSC (bits[5:0]) is showing 0b110101, it means:

    0b110101 IMPLEMENTATION DEFINED fault (Unsupported Exclusive or Atomic access).

    Further info about this encoding may be found in a core's TRM as it's IMPLEMENTATION DEFINED.

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  • 0

    The register specification of ESR_ELx can be found in the Arm ARMv8-A (see the link below).

    developer.arm.com/.../

    For example, ESL_EL1 can be found in D19.2.37 ESR_EL1, Exception Syndrome Register (EL1) of the Arm ARMv8-A (J.a) above.

    Since EC (bits [31:26]) is showing 0b100101 in your case, it means:

    EC == 0b100101
    Data Abort exception taken without a change in Exception level.
    Used for MMU faults generated by data accesses, alignment faults other than those
    caused by Stack Pointer misalignment, and synchronous External aborts, including
    synchronous parity or ECC errors. Not used for debug-related exceptions.

    And, DFSC (bits[5:0]) is showing 0b110101, it means:

    0b110101 IMPLEMENTATION DEFINED fault (Unsupported Exclusive or Atomic access).

    Further info about this encoding may be found in a core's TRM as it's IMPLEMENTATION DEFINED.

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