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What is in the March 2021 Maintenance Release of Morello Platform (FVP) model?

Arm made a maintenance release of the Morello Platform Model (FVP) on 1 March 2021. What is in this release?

  • The Morello FVP 1.2 release includes a few modifications to the model package dependencies to improve the installation process and running the model. On the model side, the FVP includes a few clock frequency alignments required for different peripherals, and we've also added a few patches for allowing GPU support in Android 10. Lastly, the Rainier CPU​ model has been updated with enhancements, alignments, and bug fixes that have been captured on the release notes.

    Here are details of the updates and changes;

    1 - Package enhancements:

    • Fixed the --show-files option on the installation script.
    • The model package name now matches the --version result from the model.
    • The RPATH in the plugins' binary correctly points to the runtime library folder ('fmtplib') provided with the package.
    • The 32-bit runtime libraries have been removed because they're not required.
    • The script was fixed but removed because it is not required since the RPATH is now fixed.
    • FVP reference guide has been updated: adds the correct folder structure and removes script usage according to the above-mentioned points.

    2 - FVP SoC and Board alignments:

    • The RTC clock is correctly set to 1Hz but modifiable via parameter. This solution allows supporting CheriBSD that uses the RTC as a fast 'counter', otherwise the bootloader would take around 20 minutes to start booting the OS.
    • The DPU 50Hz clock is now set to 50Hz. Seems this doesn't impact on how the model works but aligns with the real HW frequency.
    • The Reference counter parameters have been exposed to the user to allow improving the counter frequency when running the SW stack on an expected 'slow' model.
    • Added GPU updates for supporting Android 10. 

    3 - Rainier CPU model changes and improvements:

    • Implemented changes in Morello REL-01 (4): D1314
    • Adjusted priorities of Page table LC or SC permission violation faults, Unsupported atomic update faults caused by CDBM updates, and Unsupported      LDCT or SDCT to Device or Non-cacheable faults relative to other faults to better match the Rainier CPU.
    • Fixed issues with capability checks of PCC when overflowing the top of the address space by sequential execution.
    • Fixed SPSR_ELx values on illegal exception return to AArch32.
    • Fixed issue with CPUACTLR_EL1[22] not affecting the STLXP instruction. 
    • Fixed issue with chicken switches in CPUACTLR* not preserving their value following a write.
    • Fixed issue with priority of Capability tag fault on an exception return to a capability with an invalid exponent.
    • Fixed some implementation-defined system registers which should ignore writes but were incorrectly faulting on a write.
    • Fixed the value of ESR_ELx.FnV on Synchronous external aborts. 
    • Fixed the address reported in FAR_ELx on some watchpoints to match the Rainier CPU.
    • Fixed the value of PMEVTYPER*.MT.