Hello everyone.
I have a working project under Keil, I can compile, run, debug etc... It uses the soft device from Nordic + my application. I changed the entire architecture of the project and migrated it in vscode with CMake. I integrated ARMCC toolchain in vscode. I can compile, but when I launch a debug session, I have this warning :
I am using Cortex Debug extension, which uses GDB.
RW_IRAM1 is indeed outside the load region in my scatter file :
; ************************************************************* ; *** Scatter-Loading Description File generated by uVision *** ; ************************************************************* LR_IROM1 0x00026000 0x00051FFF { ; load region size_region ER_IROM1 0x00026000 0x00051FFF { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) } RW_IRAM1 0x200025E8 0x0000D868 { ; RW data .ANY (+RW +ZI) } }
When I debug with Keil, it goes well. I tried to create two separated load regions, one for rom, one for ram. I can debug, but the program doesn't run anymore (I reported the changes in the scatter file in keil, and the working program doesn't work). Sttrange thing is : when I try this with a trivial application (blinky led) it works, so I assume problem comes with the use of the soft device.
Does anyone knows how to make things works? I am running out of ideas here. I can provide a lot of things (compilation commands, link commands, debug commands, chunks of .map file etc ....)
Hello,
Though I have not replicated this issue myself, I found the below on Stack Overflow which suggests a workaround, to edit the ELF data to the load address rather than the execution address.
https://stackoverflow.com/questions/49508277/warning-loadable-section-my-section-outside-of-elf-segments
Though probably unrelated to this issue, I notice in your scatter file that you specify the load region size as 0x51FFF.This should likely be 0x52000, (or 0x52000 - 0x26000 = 0x2C000).
Hi, thank you for your answer. I saw this post and there are 2 key differences : 1) his RO section is located in RAM while mine is in Flash 2) his RW section and ZI section are separated, while in my scatter file, it has the same name, so I can't remove only my RW after having merged it like he des (I tried). I could separate my RW and ZI section but I would have to choose a startinf adress for the ZI section, far enough from the RW section so the linker doesn't complain for lack of space. The downside of this is I loose some memory. What I did : considering that RW section was indeed out of bound regarding the declared load region (26000 + 51FFF << 200025E8) I created two load regions : one for rom, one for ram. Then I create the hex file with fromelf and the option --i32combined. Now everyone is happy, my board, and GDB :).