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Counter max not correct when using Sysclock config

Hello,

I am experimenting with the logic analyser to display a counter value.

I am using an STM32F429I board and set the frequency to 100 Mhz.

When I visualise the value of the counter in the logic analyser I am getting big value where I expect value between 0 and 100

In the picture below the counter is 67 but the logic analyser show a big number value.

Why is this happening, did I miss anything ?

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