Greetings!
Keil uVision 5, ARM Compiler 6.12, -Os balanced, Cortex-M3. Just as an example
GPIOC->OR = (GPIOC->OR & ~0xFF) | 0x12; while(1) { u32 i = 100000; ... }
MOVS r1, #0x12 LDR r0, [r12, #0x00] BFI r0, r1, #0, #8 MOVW r1, #0x86A0 STR r0, [r12, #0x00] MOVT r1, #0x01
As you can see, there was a reordering of instructions. It is quite legal, I understand that perfectly.But how do you make the compiler not do this here? I want nothing superfluous to be wedged into the GPIOC->OR change
MOVS r1, #0x12 LDR r0, [r12, #0x00] BFI r0, r1, #0, #8 STR r0, [r12, #0x00] MOVW r1, #0x86A0 MOVT r1, #0x01
What optimizer barrier should I use and how?
Perhaps a compile-time barrier?
On gcc:
asm volatile("" ::: "memory");
There has to be a similar construct available with the tools you are using.
Edit: Since we want "nothing superfluous" to be wedged, even the compiler barrier may not work in all cases. There's still a chance that an instruction that isn't a memory access can be wedged in-between. As mentioned elsewhere, writing one's own assembly is a solution.