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DFU Bootloader cannot jump to application

Hi All,

I am using STR912FAW44 and keil MDK to develop the DFU bootloader. When the program jumps to Application, it hangs there. I set up a breakpoint before jump, I find it always goes to undefined handler. I wonder what causes to go to the undefined handler. Greatly appreciate any suggestions.


    FMI->BBSR   = 0x0;
    FMI->NBBSR  = 0x6;
    FMI->BBADR  = 0x400000 >> 2;
    FMI->NBBADR = 0x0 ;
    /* Jump to the user application and execute it */
    Jump_To_Application = (pFunction) 0x00;

    Jump_To_Application();   (set breakpoint here)

Best Regards,

Lillian

Parents
  • HI,

    I cannot post long message. Here is the second part of application stratup file.

    
                    PRESERVE8
                    AREA    Reset, CODE, READONLY
                    ARM
    
    Vectors         LDR     PC, Reset_Addr
                    LDR     PC, Undef_Addr
                    LDR     PC, SWI_Addr
                    LDR     PC, PAbt_Addr
                    LDR     PC, DAbt_Addr
                    NOP                         ; Reserved Vector
                    LDR     PC, IRQ_Addr
     ;               LDR     PC, [PC, #-0x0FF0]
                    LDR     PC, FIQ_Addr
    
                    IF      LEH_SETUP <> 0
                    EXTERN  UndefHandler
                    EXTERN  SWIHandler
                    EXTERN  PAbtHandler
                    EXTERN  DAbtHandler
                    EXTERN  IRQHandler
                    EXTERN  FIQHandler
                    ENDIF
    
    Reset_Addr      DCD     Reset_Handler
    Undef_Addr      DCD     UndefHandler
    SWI_Addr        DCD     SWIHandler
    PAbt_Addr       DCD     PAbtHandler
    DAbt_Addr       DCD     DAbtHandler
                    DCD     0                   ; Reserved Address
    IRQ_Addr        DCD     IRQHandler
    FIQ_Addr        DCD     FIQHandler
    
    
                    IF      LEH_SETUP = 0
    
    UndefHandler    B       UndefHandler
    SWIHandler      B       SWIHandler
    PAbtHandler     B       PAbtHandler
    DAbtHandler     B       DAbtHandler
    IRQHandler      B       IRQHandler
    FIQHandler      B       FIQHandler
    
                    ENDIF
    
    ; Reset Handler
    
                    EXPORT  Reset_Handler
    Reset_Handler
    
                    NOP     ; Wait for OSC stabilization
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
    
      IF BUFFRED_MODE_SETUP ==1
        ; BUFFERED_Mode
      ; -------------------------------------------------------------------------------
      ; Description  :   Enable the Buffered mode.
      ;                  When enable, just enable the buffered define on the 91x_conf.h
      ; -------------------------------------------------------------------------------
    
            MRC     p15, 0, r0, c1, c0, 0   ; Read CP15 register 1 into r0
            ORR     r0, r0, #0x8            ; Enable Write Buffer on AHB
            MCR     p15, 0, r0, c1, c0, 0   ; Write CP15 register 1
      ENDIF
    
    
    
    ; Setup System Configuration (and SRAM Size)
                    IF      SCR0_SETUP == 1
    
                    LDR     R0, =SCU_BASE
                    LDR     R1, =SCU_SCR0_Val
                    STR     R1, [R0, #SCU_SCR0_OFS]
                    ORR     R1, #0x00000200
                    STR     R1, [R0, #SCU_SCR0_OFS]
    
                    ENDIF
    
    
    ; Setup Flash Memory Interface (FMI)
                    IF      FMI_SETUP == 1
    
                    LDR     R0, =FMI_BASE
                    LDR     R1, =FMI_BBSR_Val
                    STR     R1, [R0, #FMI_BBSR_OFS]
                    LDR     R1, =FMI_NBBSR_Val
                    STR     R1, [R0, #FMI_NBBSR_OFS]
                    LDR     R1, =(FMI_BBADR_Val:SHR:2)
                    STR     R1, [R0, #FMI_BBADR_OFS]
                    LDR     R1, =(FMI_NBBADR_Val:SHR:2)
                    STR     R1, [R0, #FMI_NBBADR_OFS]
                    LDR     R2, =FMI_CR_Val
                    STR     R2, [R0, #FMI_CR_OFS]
    
                    ; Write "Write flash configuration" command (60h)
                    MOV     R0, R1, LSL #2
                    MOV     R1, #0x60
                    STRH    R1, [R0, #0]
    
                    ; Write "Write flash configuration confirm" command (03h)
                    LDR     R2, =(FLASH_CFG_Val:SHL:2)
                    ADD     R0, R0, R2
                    MOV     R1, #0x03
                    STRH    R1, [R0, #0]
    
                    ENDIF
    
    
    ; Setup Clock
                    IF      CLOCK_SETUP == 1
    
                    LDR     R0, =SCU_BASE
                    LDR     R1, =0x00020002
                    STR     R1, [R0, #SCU_CLKCNTR_OFS]    ; Select OSC as clk src
    
                    NOP     ; Wait for OSC stabilization
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
    
                    LDR     R1, =0x0003C019               ; PLL to default
                    STR     R1, [R0, #SCU_PLLCONF_OFS]
                    LDR     R1, =SCU_PLLCONF_Val          ; PLL to requested value
                    STR     R1, [R0, #SCU_PLLCONF_OFS]
    
                    ; Wait until PLL is stabilized (if PLL enabled)
                    IF      (SCU_PLLCONF_Val:AND:0x80000) != 0
    PLL_Loop        LDR     R2, [R0, #SCU_SYSSTAT_OFS]
                    ANDS    R2, R2, #SYSSTAT_LOCK
                    BEQ     PLL_Loop
                    ENDIF
    
                    LDR     R1, =SCU_CLKCNTR_Val          ; Setup clock control
                    STR     R1, [R0, #SCU_CLKCNTR_OFS]
    
                    LDR     R1, =SCU_PCGR0_Val            ; Enable clock gating
                    STR     R1, [R0, #SCU_PCGR0_OFS]
                    LDR     R1, =SCU_PCGR1_Val
                    STR     R1, [R0, #SCU_PCGR1_OFS]
    
                    ENDIF
    
    


    Thanks

    Lillian

Reply
  • HI,

    I cannot post long message. Here is the second part of application stratup file.

    
                    PRESERVE8
                    AREA    Reset, CODE, READONLY
                    ARM
    
    Vectors         LDR     PC, Reset_Addr
                    LDR     PC, Undef_Addr
                    LDR     PC, SWI_Addr
                    LDR     PC, PAbt_Addr
                    LDR     PC, DAbt_Addr
                    NOP                         ; Reserved Vector
                    LDR     PC, IRQ_Addr
     ;               LDR     PC, [PC, #-0x0FF0]
                    LDR     PC, FIQ_Addr
    
                    IF      LEH_SETUP <> 0
                    EXTERN  UndefHandler
                    EXTERN  SWIHandler
                    EXTERN  PAbtHandler
                    EXTERN  DAbtHandler
                    EXTERN  IRQHandler
                    EXTERN  FIQHandler
                    ENDIF
    
    Reset_Addr      DCD     Reset_Handler
    Undef_Addr      DCD     UndefHandler
    SWI_Addr        DCD     SWIHandler
    PAbt_Addr       DCD     PAbtHandler
    DAbt_Addr       DCD     DAbtHandler
                    DCD     0                   ; Reserved Address
    IRQ_Addr        DCD     IRQHandler
    FIQ_Addr        DCD     FIQHandler
    
    
                    IF      LEH_SETUP = 0
    
    UndefHandler    B       UndefHandler
    SWIHandler      B       SWIHandler
    PAbtHandler     B       PAbtHandler
    DAbtHandler     B       DAbtHandler
    IRQHandler      B       IRQHandler
    FIQHandler      B       FIQHandler
    
                    ENDIF
    
    ; Reset Handler
    
                    EXPORT  Reset_Handler
    Reset_Handler
    
                    NOP     ; Wait for OSC stabilization
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
    
      IF BUFFRED_MODE_SETUP ==1
        ; BUFFERED_Mode
      ; -------------------------------------------------------------------------------
      ; Description  :   Enable the Buffered mode.
      ;                  When enable, just enable the buffered define on the 91x_conf.h
      ; -------------------------------------------------------------------------------
    
            MRC     p15, 0, r0, c1, c0, 0   ; Read CP15 register 1 into r0
            ORR     r0, r0, #0x8            ; Enable Write Buffer on AHB
            MCR     p15, 0, r0, c1, c0, 0   ; Write CP15 register 1
      ENDIF
    
    
    
    ; Setup System Configuration (and SRAM Size)
                    IF      SCR0_SETUP == 1
    
                    LDR     R0, =SCU_BASE
                    LDR     R1, =SCU_SCR0_Val
                    STR     R1, [R0, #SCU_SCR0_OFS]
                    ORR     R1, #0x00000200
                    STR     R1, [R0, #SCU_SCR0_OFS]
    
                    ENDIF
    
    
    ; Setup Flash Memory Interface (FMI)
                    IF      FMI_SETUP == 1
    
                    LDR     R0, =FMI_BASE
                    LDR     R1, =FMI_BBSR_Val
                    STR     R1, [R0, #FMI_BBSR_OFS]
                    LDR     R1, =FMI_NBBSR_Val
                    STR     R1, [R0, #FMI_NBBSR_OFS]
                    LDR     R1, =(FMI_BBADR_Val:SHR:2)
                    STR     R1, [R0, #FMI_BBADR_OFS]
                    LDR     R1, =(FMI_NBBADR_Val:SHR:2)
                    STR     R1, [R0, #FMI_NBBADR_OFS]
                    LDR     R2, =FMI_CR_Val
                    STR     R2, [R0, #FMI_CR_OFS]
    
                    ; Write "Write flash configuration" command (60h)
                    MOV     R0, R1, LSL #2
                    MOV     R1, #0x60
                    STRH    R1, [R0, #0]
    
                    ; Write "Write flash configuration confirm" command (03h)
                    LDR     R2, =(FLASH_CFG_Val:SHL:2)
                    ADD     R0, R0, R2
                    MOV     R1, #0x03
                    STRH    R1, [R0, #0]
    
                    ENDIF
    
    
    ; Setup Clock
                    IF      CLOCK_SETUP == 1
    
                    LDR     R0, =SCU_BASE
                    LDR     R1, =0x00020002
                    STR     R1, [R0, #SCU_CLKCNTR_OFS]    ; Select OSC as clk src
    
                    NOP     ; Wait for OSC stabilization
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
                    NOP
    
                    LDR     R1, =0x0003C019               ; PLL to default
                    STR     R1, [R0, #SCU_PLLCONF_OFS]
                    LDR     R1, =SCU_PLLCONF_Val          ; PLL to requested value
                    STR     R1, [R0, #SCU_PLLCONF_OFS]
    
                    ; Wait until PLL is stabilized (if PLL enabled)
                    IF      (SCU_PLLCONF_Val:AND:0x80000) != 0
    PLL_Loop        LDR     R2, [R0, #SCU_SYSSTAT_OFS]
                    ANDS    R2, R2, #SYSSTAT_LOCK
                    BEQ     PLL_Loop
                    ENDIF
    
                    LDR     R1, =SCU_CLKCNTR_Val          ; Setup clock control
                    STR     R1, [R0, #SCU_CLKCNTR_OFS]
    
                    LDR     R1, =SCU_PCGR0_Val            ; Enable clock gating
                    STR     R1, [R0, #SCU_PCGR0_OFS]
                    LDR     R1, =SCU_PCGR1_Val
                    STR     R1, [R0, #SCU_PCGR1_OFS]
    
                    ENDIF
    
    


    Thanks

    Lillian

Children
  • Hi,

    The third part of application startup file.

     ; Setup Peripheral Reset
                    IF      P_RESET_SETUP != 0
                    LDR     R1, =SCU_PRR0_Val
                    STR     R1, [R0, #SCU_PRR0_OFS]
                    LDR     R1, =SCU_PRR1_Val
                    STR     R1, [R0, #SCU_PRR1_OFS]
                    ENDIF
    
    ; Setup Stack for each mode
    
                    LDR     R0, =Stack_Top
    
    ;  Enter Undefined Instruction Mode and set its Stack Pointer
                    MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                    MOV     SP, R0
                    SUB     R0, R0, #UND_Stack_Size
    
    ;  Enter Abort Mode and set its Stack Pointer
                    MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                    MOV     SP, R0
                    SUB     R0, R0, #ABT_Stack_Size
    
    ;  Enter FIQ Mode and set its Stack Pointer
                    MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                    MOV     SP, R0
                    SUB     R0, R0, #FIQ_Stack_Size
    
    ;  Enter IRQ Mode and set its Stack Pointer
                    MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                    MOV     SP, R0
                    SUB     R0, R0, #IRQ_Stack_Size
    
    ;  Enter Supervisor Mode and set its Stack Pointer
                    MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                    MOV     SP, R0
                    SUB     R0, R0, #SVC_Stack_Size
    
    ;  Enter User Mode and set its Stack Pointer
                    MSR     CPSR_c, #Mode_USR
                    MOV     SP, R0
                    SUB     SL, SP, #USR_Stack_Size
    
    ; Enter the C code
    
                    IMPORT  __main
                    LDR     R0, =__main
                    BX      R0
    
    ; User Initial Stack & Heap
                    AREA    |.text|, CODE, READONLY
    
                    IMPORT  __use_two_region_memory
                    EXPORT  __user_initial_stackheap
    __user_initial_stackheap
    
                    LDR     R0, =  Heap_Mem
                    LDR     R1, =(Stack_Mem + USR_Stack_Size)
                    LDR     R2, = (Heap_Mem +      Heap_Size)
                    LDR     R3, = Stack_Mem
                    BX      LR
    
    
                    END
    
    

    Thanks

    Lillian

  • Sorry I currently don't have any more suggestions.

    I think you will have to set through the assembler to see when it actually jumps to undefined handler.

  • Hi All,

    Finally, my DFU bootloader can jump to the application. However, new issues come out.

    1. The application works fine as loaded by uLink2 without DFU bootloader.
    2. Load the DFU bootloader and it jumps to the application. But the application will crash after running a while.

    My application includes FIQ timer and USB CDC.

    I wonder it may be caused by the stack size and increase them, but no luck.

    The stack size for DFU bootloader is set as followes.

    UND_Stack_Size  EQU     0x00000040
    SVC_Stack_Size  EQU     0x00000040;0x00000008
    ABT_Stack_Size  EQU     0x00000040
    FIQ_Stack_Size  EQU     0x00001800
    IRQ_Stack_Size  EQU     0x00001800
    USR_Stack_Size  EQU     0x00002000
    
    ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ 
                             FIQ_Stack_Size + IRQ_Stack_Size)
    
                    AREA    STACK, NOINIT, READWRITE, ALIGN=3
    
    Stack_Mem       SPACE   USR_Stack_Size
    __initial_sp    SPACE   ISR_Stack_Size
    Stack_Top
    
    
    ;// <h> Heap Configuration
    ;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
    ;// </h>
    
    Heap_Size       EQU     0x00000400;0x00000200
    
                    AREA    HEAP, NOINIT, READWRITE, ALIGN=3
    __heap_base
    Heap_Mem        SPACE   Heap_Size
    __heap_limit
    

    The stack size for application is

    UND_Stack_Size  EQU     0x00000020
    SVC_Stack_Size  EQU     0x00000ff0;0x00000008
    ABT_Stack_Size  EQU     0x00000020
    FIQ_Stack_Size  EQU     0x00001200
    IRQ_Stack_Size  EQU     0x00000400
    USR_Stack_Size  EQU     0x00001000
    
    ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ 
                             FIQ_Stack_Size + IRQ_Stack_Size)
    
                    AREA    STACK, NOINIT, READWRITE, ALIGN=3
    
    Stack_Mem       SPACE   USR_Stack_Size
    __initial_sp    SPACE   ISR_Stack_Size
    Stack_Top
    
    
    ;// <h> Heap Configuration
    ;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
    ;// </h>
    
    Heap_Size       EQU     0x00000400
    
                    AREA    HEAP, NOINIT, READWRITE, ALIGN=3
    __heap_base
    Heap_Mem        SPACE   Heap_Size
    __heap_limit
    

    Please help me. What may results in the issues above. Appreciate any suggestions.

    Best Regards,

    Lillian

  • For a NXP LPC23xx:

    When the bootloader jumps to the application, it should be in the privilege mode; otherwise the application will fail to set the stack.