Hi All,
I am using STR912FAW44 and keil MDK to develop the DFU bootloader. When the program jumps to Application, it hangs there. I set up a breakpoint before jump, I find it always goes to undefined handler. I wonder what causes to go to the undefined handler. Greatly appreciate any suggestions.
FMI->BBSR = 0x0; FMI->NBBSR = 0x6; FMI->BBADR = 0x400000 >> 2; FMI->NBBADR = 0x0 ; /* Jump to the user application and execute it */ Jump_To_Application = (pFunction) 0x00; Jump_To_Application(); (set breakpoint here)
Best Regards,
Lillian
Lillian,
You must execute this from RAM. If you try and execute it from Flash in the STR9 it will fail, as you will have swapped the flash banks before the code is executed.
Stuart
HI Stuart,
Thank you very much for your help.
I did put the code below in RAM
// before change mapping, disable all VIC ints VIC0->INTECR = 0xff; VIC1->INTECR = 0xff; FMI->BBSR = 0x0; FMI->NBBSR = 0x6; FMI->BBADR = 0x400000 >> 2; FMI->NBBADR = 0x0 ; /* Jump to the user application and execute it */ Jump_To_Application = (pFunction) 0x00; Jump_To_Application();
I doubt the start up file is something wrong.
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs Mode_USR EQU 0x10 Mode_FIQ EQU 0x11 Mode_IRQ EQU 0x12 Mode_SVC EQU 0x13 Mode_ABT EQU 0x17 Mode_UND EQU 0x1B Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled UND_Stack_Size EQU 0x00000020 SVC_Stack_Size EQU 0x00000008 ABT_Stack_Size EQU 0x00000020 FIQ_Stack_Size EQU 0x00001200 IRQ_Stack_Size EQU 0x00000400 USR_Stack_Size EQU 0x00001000 ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ FIQ_Stack_Size + IRQ_Stack_Size) AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE USR_Stack_Size __initial_sp SPACE ISR_Stack_Size Stack_Top ;// <h> Heap Configuration ;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> ;// </h> Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit ; --- STR9X SCU specific definitions SCU_BASE_Address EQU 0x5C002000 ; SCU Base Address SCU_SCR0_OFST EQU 0x00000034 ; System Configuration Register 0 Offset ; --- STR9X FMI specific definitions FMI_BASE_Address EQU 0x54000000 ; FMI Base Address FMI_BBSR_OFST EQU 0x00000000 ; Boot Bank Size Register offset FMI_NBBSR_OFST EQU 0x00000004 ; Non-boot Bank Size Register offset FMI_BBADR_OFST EQU 0x0000000C ; Boot Bank Base Address Register offset FMI_NBBADR_OFST EQU 0x00000010 ; Non-boot Bank Base Address Register offset FMI_CR_OFST EQU 0x00000018 ; Control Register offset FMI_SETUP EQU 1 FMI_CR_Val EQU 0x00000018 FMI_BBSR_Val EQU 0x00000000 FMI_BBADR_Val EQU 0x00000000 FMI_NBBSR_Val EQU 0x00000006 FMI_NBBADR_Val EQU 0x00400000;0x00080000 FLASH_CFG_Val EQU 0x00000000
;--------------------------------------------------------------- ; Reset Handler ;--------------------------------------------------------------- PRESERVE8 ; Area Definition and Entry Point ; Startup Code must be linked first at Address at which it expects to run. AREA Init, CODE, READONLY ARM EXPORT Reset_Handler Reset_Handler LDR pc, =NextInst NextInst ;; ------------------------------------------------------------------------------ ; Description : Enable the Buffered mode. ; To use buffered mode access you have to uncomment Buffered ; define on the 91x_conf.h file ; ------------------------------------------------------------------------------ MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0 ORR r0, r0, #0x8 ; Enable Write Buffer on AHB MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1 ;------------------------------------------------------------------------------ ; Description : Write Buffer in ITCM may cause the Flash “write then read” ; command order reversed and cause flash error. ; To maintain the right order, bit 18 (Instruction TCM order bit) ; in the Configuration Registers of the ARM966E-S core must be set. ; ------------------------------------------------------------------------------ MOV r0, #0x40000 MCR p15,0x1,r0,c15,c1,0 ;------------------------------------------------------------------------------ ; Description : FMI Registers configuration depending on the Flash size selected, ; and the boot bank. ; ; After reset, the application program has to write the size and start ; address of Bank 1 in the FMI_BBSR and FMI_BBADR registers and the size and ; start address of Bank 0 in the FMI_NBBSR and FMI_NBBADR registers. ; ------------------------------------------------------------------------------ IF FMI_SETUP == 1 LDR R6, =FMI_BASE_Address LDR R7, = FMI_BBSR_Val ; BOOT BANK Size= STR R7, [R6, #FMI_BBSR_OFST] ; (2^BOOT_BANK_Size) * 32KBytes LDR R7, = FMI_NBBSR_Val ; NON BOOT BANK Size = STR R7, [R6, #FMI_NBBSR_OFST] ; (2^NON_BOOT_BANK_Size) * 8KBytes LDR R7, =FMI_BBADR_Val ; BOOT BANK Address MOV R7, R7 ,LSR #0x2 STR R7, [R6, #FMI_BBADR_OFST] LDR R7, =FMI_NBBADR_Val ; BOOT BANK Address MOV R7, R7 ,LSR #0x2 STR R7, [R6, #FMI_NBBADR_OFST] LDR R7, = 0x19;0x00001010;0x19 ; Enable Both banks STR R7, [R6, #FMI_CR_OFST] ENDIF
Please help me. I feel very frustrated.
Thanks
In my system I need two startup files. 1 for bootloader and 1 for application.
The boot-loader startup sets up the flash banks and executes. Eventually the boot-loader while executing from RAM reconfigures the flash banks and jumps to the application now located at 0x0.
The application startup however does not change any flash bank settings otherwise this can undo the flash settings configured by the bootloader previously.
Hi Stuart,
I have two start up files as well. One is for Bootlaoder like the above I post. Another is for Application as follows:
BUFFRED_MODE_SETUP EQU 1 ; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs Mode_USR EQU 0x10 Mode_FIQ EQU 0x11 Mode_IRQ EQU 0x12 Mode_SVC EQU 0x13 Mode_ABT EQU 0x17 Mode_UND EQU 0x1B Mode_SYS EQU 0x1F I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled UND_Stack_Size EQU 0x00000008 SVC_Stack_Size EQU 0x00000008 ABT_Stack_Size EQU 0x00000000 FIQ_Stack_Size EQU 0x00000000 IRQ_Stack_Size EQU 0x00000400 USR_Stack_Size EQU 0x00000400 Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size) AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size Stack_Top EQU Stack_Mem + Stack_Size Heap_Size EQU 0x00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=3 Heap_Mem SPACE Heap_Size SCR0_SETUP EQU 1 SCU_SCR0_Val EQU 0x00000196 ; Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses) FMI_BASE EQU 0x54000000 ; FMI Base Address (non-buffered) FMI_BBSR_OFS EQU 0x00 ; Boot Bank Size Register FMI_NBBSR_OFS EQU 0x04 ; Non-boot Bank Size Register FMI_BBADR_OFS EQU 0x0C ; Boot Bank Base Address Register FMI_NBBADR_OFS EQU 0x10 ; Non-boot Bank Base Address Register FMI_CR_OFS EQU 0x18 ; Control Register FMI_SETUP EQU 0 FMI_CR_Val EQU 0x00000018 FMI_BBSR_Val EQU 0x00000004 FMI_BBADR_Val EQU 0x00000000 FMI_NBBSR_Val EQU 0x00000002 FMI_NBBADR_Val EQU 0x00400000 FLASH_CFG_Val EQU 0x00000000 ; System Control Unit (SCU) definitions SCU_BASE EQU 0x5C002000 ; SCU Base Address (non-buffered) SCU_CLKCNTR_OFS EQU 0x00 ; Clock Control register Offset SCU_PLLCONF_OFS EQU 0x04 ; PLL Configuration register Offset SCU_SYSSTAT_OFS EQU 0x08 ; System Status Register Offset SCU_PCGR0_OFS EQU 0x14 ; Peripheral Clock Gating Register 0 Offset SCU_PCGR1_OFS EQU 0x18 ; Peripheral Clock Gating Register 1 Offset SCU_PRR0_OFS EQU 0x1C ; Peripheral Reset Register 0 Offset SCU_PRR1_OFS EQU 0x20 ; Peripheral Reset Register 1 Offset SCU_SCR0_OFS EQU 0x34 ; System Configuration Register 0 Offset ; Constants SYSSTAT_LOCK EQU 0x01 ; PLL Lock Status CLOCK_SETUP EQU 0 SCU_CLKCNTR_Val EQU 0x00020000 SCU_PLLCONF_Val EQU 0x000BC019 SCU_PCGR0_Val EQU 0x000000DB SCU_PCGR1_Val EQU 0x00000000 P_RESET_SETUP EQU 0 SCU_PRR0_Val EQU 0x00001053 SCU_PRR1_Val EQU 0x00000000 ; APB Bridge 1 & 2 definitions (Peripherals) APB0_BUF_BASE EQU 0x48001802 ; APB Bridge 0 Buffered Base Address APB0_NBUF_BASE EQU 0x58000000 ; APB Bridge 0 Non-buffered Base Address APB1_BUF_BASE EQU 0x4C000000 ; APB Bridge 1 Buffered Base Address APB1_NBUF_BASE EQU 0x5C000000 ; APB Bridge 1 Non-buffered Base Address LEH_SETUP EQU 1
I disbale the FMI setting at the start file of application. Also, for the test purpose, I program a simple application which doesn't have any interrupts. However, I have no luck and the program still jumps to undefined handler.
Help please!!!!!!!!!!!!!!
Highly appreciate any suggestions.
HI,
I cannot post long message. Here is the second part of application stratup file.
PRESERVE8 AREA Reset, CODE, READONLY ARM Vectors LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector LDR PC, IRQ_Addr ; LDR PC, [PC, #-0x0FF0] LDR PC, FIQ_Addr IF LEH_SETUP <> 0 EXTERN UndefHandler EXTERN SWIHandler EXTERN PAbtHandler EXTERN DAbtHandler EXTERN IRQHandler EXTERN FIQHandler ENDIF Reset_Addr DCD Reset_Handler Undef_Addr DCD UndefHandler SWI_Addr DCD SWIHandler PAbt_Addr DCD PAbtHandler DAbt_Addr DCD DAbtHandler DCD 0 ; Reserved Address IRQ_Addr DCD IRQHandler FIQ_Addr DCD FIQHandler IF LEH_SETUP = 0 UndefHandler B UndefHandler SWIHandler B SWIHandler PAbtHandler B PAbtHandler DAbtHandler B DAbtHandler IRQHandler B IRQHandler FIQHandler B FIQHandler ENDIF ; Reset Handler EXPORT Reset_Handler Reset_Handler NOP ; Wait for OSC stabilization NOP NOP NOP NOP NOP NOP NOP IF BUFFRED_MODE_SETUP ==1 ; BUFFERED_Mode ; ------------------------------------------------------------------------------- ; Description : Enable the Buffered mode. ; When enable, just enable the buffered define on the 91x_conf.h ; ------------------------------------------------------------------------------- MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0 ORR r0, r0, #0x8 ; Enable Write Buffer on AHB MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1 ENDIF ; Setup System Configuration (and SRAM Size) IF SCR0_SETUP == 1 LDR R0, =SCU_BASE LDR R1, =SCU_SCR0_Val STR R1, [R0, #SCU_SCR0_OFS] ORR R1, #0x00000200 STR R1, [R0, #SCU_SCR0_OFS] ENDIF ; Setup Flash Memory Interface (FMI) IF FMI_SETUP == 1 LDR R0, =FMI_BASE LDR R1, =FMI_BBSR_Val STR R1, [R0, #FMI_BBSR_OFS] LDR R1, =FMI_NBBSR_Val STR R1, [R0, #FMI_NBBSR_OFS] LDR R1, =(FMI_BBADR_Val:SHR:2) STR R1, [R0, #FMI_BBADR_OFS] LDR R1, =(FMI_NBBADR_Val:SHR:2) STR R1, [R0, #FMI_NBBADR_OFS] LDR R2, =FMI_CR_Val STR R2, [R0, #FMI_CR_OFS] ; Write "Write flash configuration" command (60h) MOV R0, R1, LSL #2 MOV R1, #0x60 STRH R1, [R0, #0] ; Write "Write flash configuration confirm" command (03h) LDR R2, =(FLASH_CFG_Val:SHL:2) ADD R0, R0, R2 MOV R1, #0x03 STRH R1, [R0, #0] ENDIF ; Setup Clock IF CLOCK_SETUP == 1 LDR R0, =SCU_BASE LDR R1, =0x00020002 STR R1, [R0, #SCU_CLKCNTR_OFS] ; Select OSC as clk src NOP ; Wait for OSC stabilization NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP LDR R1, =0x0003C019 ; PLL to default STR R1, [R0, #SCU_PLLCONF_OFS] LDR R1, =SCU_PLLCONF_Val ; PLL to requested value STR R1, [R0, #SCU_PLLCONF_OFS] ; Wait until PLL is stabilized (if PLL enabled) IF (SCU_PLLCONF_Val:AND:0x80000) != 0 PLL_Loop LDR R2, [R0, #SCU_SYSSTAT_OFS] ANDS R2, R2, #SYSSTAT_LOCK BEQ PLL_Loop ENDIF LDR R1, =SCU_CLKCNTR_Val ; Setup clock control STR R1, [R0, #SCU_CLKCNTR_OFS] LDR R1, =SCU_PCGR0_Val ; Enable clock gating STR R1, [R0, #SCU_PCGR0_OFS] LDR R1, =SCU_PCGR1_Val STR R1, [R0, #SCU_PCGR1_OFS] ENDIF
Hi,
The third part of application startup file.
; Setup Peripheral Reset IF P_RESET_SETUP != 0 LDR R1, =SCU_PRR0_Val STR R1, [R0, #SCU_PRR0_OFS] LDR R1, =SCU_PRR1_Val STR R1, [R0, #SCU_PRR1_OFS] ENDIF ; Setup Stack for each mode LDR R0, =Stack_Top ; Enter Undefined Instruction Mode and set its Stack Pointer MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #UND_Stack_Size ; Enter Abort Mode and set its Stack Pointer MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #ABT_Stack_Size ; Enter FIQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #FIQ_Stack_Size ; Enter IRQ Mode and set its Stack Pointer MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #IRQ_Stack_Size ; Enter Supervisor Mode and set its Stack Pointer MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit MOV SP, R0 SUB R0, R0, #SVC_Stack_Size ; Enter User Mode and set its Stack Pointer MSR CPSR_c, #Mode_USR MOV SP, R0 SUB SL, SP, #USR_Stack_Size ; Enter the C code IMPORT __main LDR R0, =__main BX R0 ; User Initial Stack & Heap AREA |.text|, CODE, READONLY IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + USR_Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR END
Sorry I currently don't have any more suggestions.
I think you will have to set through the assembler to see when it actually jumps to undefined handler.
Finally, my DFU bootloader can jump to the application. However, new issues come out.
1. The application works fine as loaded by uLink2 without DFU bootloader. 2. Load the DFU bootloader and it jumps to the application. But the application will crash after running a while.
My application includes FIQ timer and USB CDC.
I wonder it may be caused by the stack size and increase them, but no luck.
The stack size for DFU bootloader is set as followes.
UND_Stack_Size EQU 0x00000040 SVC_Stack_Size EQU 0x00000040;0x00000008 ABT_Stack_Size EQU 0x00000040 FIQ_Stack_Size EQU 0x00001800 IRQ_Stack_Size EQU 0x00001800 USR_Stack_Size EQU 0x00002000 ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ FIQ_Stack_Size + IRQ_Stack_Size) AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE USR_Stack_Size __initial_sp SPACE ISR_Stack_Size Stack_Top ;// <h> Heap Configuration ;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> ;// </h> Heap_Size EQU 0x00000400;0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit
The stack size for application is
UND_Stack_Size EQU 0x00000020 SVC_Stack_Size EQU 0x00000ff0;0x00000008 ABT_Stack_Size EQU 0x00000020 FIQ_Stack_Size EQU 0x00001200 IRQ_Stack_Size EQU 0x00000400 USR_Stack_Size EQU 0x00001000 ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ FIQ_Stack_Size + IRQ_Stack_Size) AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE USR_Stack_Size __initial_sp SPACE ISR_Stack_Size Stack_Top ;// <h> Heap Configuration ;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> ;// </h> Heap_Size EQU 0x00000400 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit
Please help me. What may results in the issues above. Appreciate any suggestions.
For a NXP LPC23xx:
When the bootloader jumps to the application, it should be in the privilege mode; otherwise the application will fail to set the stack.