Hello!
The board is built on C167CS crystal, with external RAM and flash at two separate (with individual /CS) 16-bit non-multiplexed buses. The flash is split into two 8-bit-data chips, the WRCFG is set to have normal configuration of /WR and /BHE. For the flash, MCU's address line A0 and the line /BHE are used along with single /CS for both flash chips to get access to the lower and upper bytes of flash. The (same) MCU's /WR and /RD pins are mapped both to the RAM and flash (and other periphery).
The f/w executes from the external flash (i.e. there are /RDs for the flash), and performs read/write operations to the RAM. No any write operation is being done to the flash (the f/w at this point does not re-program the flash) - i.e., if MCU's /WR is active, the flash's /CS is inactive. Using scope I see the /BHE becomes active (i.e. low) when flash's /CS is active, and /RD is active.
From the C167 manual it is not quite clear whether /BHE works with /WR signal only or with both /RD and /WR signal.
The f/w runs OK, but I need to get a confidence if my inderstanding is correct: can the /BHE be active in described situation where only /RD is performed, i.e. should /BHE be active not only for the /WR?
Thanks, Nikolay.
Thank you,
This is valid point. Unfortunately, neither in Infineon nor in ST docs there is no explicit wording or (better) timing diagram reflecting how the MCU operates with the /BHE.
Before questioning, I have had look at Hitex's Insiders' Guide (the link is www.hitex.com/.../166des19-a.html), however have not found explicit mentioning on /BHE pin functionality either. But here is an useful info, page 29. Hitex authors talk about a RAM, but it does not matter for the case: To successfully use 8-bit RAMs the user must remember that the A0 pins on the RAMs go to A1 on the 167. ... A0 is effectively redundant in such a configuration. ... When the CPU reads a word both RAMs are enabled simultaneously by /READ so that the CPU can read D0-D15 in one access across the bus. As the 166 is a 16-bit machine, all read accesses are wordwide, even byte ones - the unwanted byte is simply discarded. ... For writes to RAM some means of only enabling one of the RAMs is required, as a byte write to an even location would corrupt the associated odd byte. The traditional method of preventing this is to create individual /WRITE signals for each RAM from /BHE and A0. ...
Here again, most accent is given to the /WR operation, with /BHE not mentioned for the reads. As a summary, it is more or less evident that the /BHE is redundant for most /RDs configuration (except that one you pointed out), however is generated by MCU for both /RD and /WR which is seen in real h/w when a scope is hooked-up.
P.S. The only explicit diagram I finally found today is in the "C167CS Data Sheet V2.2" (not User Manual), pages 66-67, 69 where the /BHE is very schematically shown on timing diagram together with address lines A0...A23, for both write and read (!) accesses.
Regards, Nikolay.