I have a timer interrupt problem. When i use timer 1 & external interrupt together, i disable All interrupt and enable it again when leaving the function. If there is external interrupt, it may miss the the timer intrrupt. Am i true???
no, it is vice versa: if you disable all interrupts during timer ISR is executed, then you have a chance to miss an external interrupt if it was configured as level activated one. Regards, Oleg
So, if I want to allow both interrupt to happen even in any ISR, what should I set? Should I enable all interrupt even in the ISR to allow this?
hi, there are alot of solutions: 1) configure an external interrupt as the edge activated. This way even during EA is cleared and interrupt comes, it has been "remembered" and will be processed after you allow interrupts back via set EA. In fact, in most cases you do not need to disable interrupts with EA inside an ISR. 2) If you need with level activated external interrupt then set its priority to high level and a timer one to low level. This way even if timer ISR is being executed at moment when external interrupt comes, anyway last one is processed over timer ISR and then program continues timer ISR. Better describe your problem instead theorical questions. For theory there are many manuals/datasheets you need to read. Regards, Oleg
Hi Ivan, If you want the timer 1 and an external interrupt 0? to work even when in another ISR then you need to set the priority bit for timer 1 (PT1) and eternal interrupt 0 (PX0) as described in the Interrupt Priority (IP) Register. Please note that when the '51 is in an interrupt you dont need to clear EA as interrupts of the same priority cannot be interrupted by any other interrupt source with the same priority. Also, if you require either the timer 1 or external interrupt to be able to interrupt each others ISR's then this is a little bit harder - but not impossible to acheive. Mark.