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Hi
Does anyone have a debug-ram.ini file they are successfully using to allow debug from ext_ram on an STM32F4? Could you post it? Init/debug in SRAM or SDRAM is fine and I can change registers to suit my memory, using yours as a (great) template.
I am NOT asking for the standard internal ram debug ini.
Thanks Mark
/******************************************************************************/ /* Ext_SDRAM.ini: External SDRAM Initialization File */ /******************************************************************************/ // <<< Use Configuration Wizard in Context Menu >>> // /******************************************************************************/ /* This file is part of the uVision/ARM development tools. */ /* Copyright (c) 2005-2009 Keil Software. All rights reserved. */ /* This software may only be used under the terms of a valid, current, */ /* end user licence from KEIL for a compatible version of KEIL software */ /* development tools. Nothing else gives you the right to use this software. */ /******************************************************************************/ DEFINE CHAR Setup; DEFINE INT Entry; DEFINE LONG PMC; DEFINE LONG PIO_SD; DEFINE LONG MATRIX; DEFINE LONG SDRAMC; DEFINE LONG SDRAM; // Memory mapped peripherals address definitions PMC = 0xFFFFFC00; PIO_SD = 0xFFFFF800; MATRIX = 0xFFFFEE00; SDRAMC = 0xFFFFEA00; SDRAM = 0x20000000; FUNC void Clock_Setup (void) { if (Setup & 0x01) { // Setup clock; XTAL = 18.432000 MHz // PLLA = 96.109714 MHz // Processor Clock = 96.109714 MHz // Master Clock = 96.109714 MHz _WDWORD(PMC+ 0x20, 0x00000701); // CKGR_MOR: Enable main oscillator _sleep_(100); // Wait for stable Main Oscillator _WDWORD(PMC+ 0x28, 0x20483F0E); // CKGR_PLLAR: Configure PLL A _WDWORD(PMC+ 0x30, 0x00000000); // PMC_MCKR: PRES field _sleep_(100); // Wait for Main Master Clock ready _WDWORD(PMC+ 0x30, 0x00000002); // PMC_MCKR: all fields _sleep_(100); // Wait for Main Master Clock ready } } FUNC void SDRAM_Setup (void) { if (Setup & 0x02) { // Setup SDRAM Controller // Setup pins for SDRAM controlling (Pins PC16 .. PC31) _WDWORD(PIO_SD+0x60, 0xFFFF0000); // Disable pull-ups _WDWORD(PIO_SD+0x70, 0xFFFF0000); // Select peripheral A _WDWORD(PIO_SD+0x04, 0xFFFF0000); // Disable PIO mode _WDWORD(MATRIX+0x11C,0x00000002); // EBI_CSA: CSA1 support for SDRAM _WDWORD(SDRAMC+0x08, 0x85227259); // SDRAM Configuration _sleep_(10); _WDWORD(SDRAMC+0x00, 0x00000001); // Issue NOP Command _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAMC+0x00, 0x00000002); // Issue Precharge All Command _WDWORD(SDRAM+ 0x00, 0x00000000); _sleep_(10); _WDWORD(SDRAMC+0x00, 0x00000004); // Issue Auto-Refresh Command _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAMC+0x00, 0x00000003); // Issue Load Mode Register Command _WDWORD(SDRAM+ 0x24, 0x00000020); _WDWORD(SDRAMC+0x00, 0x00000000); // Enter Normal Mode _WDWORD(SDRAM+ 0x00, 0x00000000); _WDWORD(SDRAMC+0x04, 0x000005DD); // Refresh for SDRAM (at 96 MHz) } } FUNC void Remap (void) { if (Setup & 0x10) { _WDWORD(MATRIX+0x100,0x00000003); // MATRIX_MRCR: Remap IRAM to 0 } } FUNC void PC_Setup (void) { if (Setup & 0x40) { PC = Entry; } } FUNC void GoMain (void) { if ((Setup & 0xA0) == 0xA0) { exec("g,main"); } } // <o1.0> Clock Setup // <o1.1> SDRAM Setup // <e1.4> Remap // </e> // <e1.5> Download Program FUNC void Download (void) { if (Setup & 0x20) { // <s0.80> Command for Loading exec("LOAD Ext_SDRAM\\Blinky.axf INCREMENTAL"); } } // </e> // <e0.6> Setup Program Counter to Entry Point // <o1> Program Entry Point <0x0-0xFFFFFFFF> // </e> // <e.7> Execute Program untill Main Function // </e> Setup = 0xF3; Entry = 0x20000000; Clock_Setup(); SDRAM_Setup(); Remap(); Download(); PC_Setup(); GoMain();