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Dual core debug of NXP LPC4000

Prajagop Prasanth

I am referring to this article: http://www.keil.com/pr/article/1227.htm

I was wondering why there is no support for a single session (Keil window) debug? Why do I have to open two windows, why can't the debug be merged? Won't I have issues when something fails with both the cores active?

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  • 0

    Because otherwise you'd get people saying, "Why is it all crammed in to one window? That makes it really cramped. It'd be so much easier to have two separate windows" ... ?

    I guess you just can't please all of the people all of the time...

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  • 0

    Because otherwise you'd get people saying, "Why is it all crammed in to one window? That makes it really cramped. It'd be so much easier to have two separate windows" ... ?

    I guess you just can't please all of the people all of the time...

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  • 0 in reply to Andy Neil

    I think it would be quite strange to try to debug two separate hardwares in the same window - what PC value are then looking at, when both processors are ticking forward?

    We are not talking about debugging two threads in the same program, but actually debugging two separate programs. How many other debuggers would debug two separate programs concurrently using a single debugger instance?

  • 0 in reply to ImPer Westermark

    I am looking at it from a debug angle, in situations where failure happens only when both the cores are running and it proves tough to crack the root cause under some specific sequence. It is quite common in slightly more complex SoCs such as those with ARM A series.

    I totally agree that if there is nothing to debug together, we rather make the environment separate.

    I am wondering if a single session debug is available in their LPCxpresso, which I believe is Eclipse based. I do not think even IAR supports this feature.

    So how do we debug multi-core failures in this case?

    • You have to keep two windows open in two monitors. Also implies you have to keep them open to see status of running or halt.
    • For all shared resources, you have to keep looking between Register / Memory windows up on either Core Halt.
    • Single stepping two cores sequentially can also be an inconvenience, when trying to reproduce the problem.

    Well, as Andrew Neil commented, you can't have everything in one plate...

  • 0 in reply to Prajagop Prasanth

    It's very much as when two processors are fitted to the same PCB and interacts with shared hardware - creativity will be needed when debugging.