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IRQn and CMSIS and µVision

Using Freescale K70 cpu with MDK 5 Rev. 5.14.
Have enabled UART0 interrupt with CMSIS: "NVIC_EnableIRQ (UART0_RX_TX_IRQn);"
Made an ISR "void UART0_RX_TX_IRQHandler (void){...}"
Get Receive Interrupts from UART0 into this ISR, so far, so good.
But: In µVision's Event Viewer window this ISR is flagged as "INT_CAN0_ORed_Message_buffer (61)"!?!.
"UART0_RX_TX_IRQn" has value 45 in CMSIS header MK70F12.h
"CAN0_ORed_Message_buffer_IRQn" has value 29 in CMSIS header MK70F12.h.
Value 61 is assigned to "CMP2_IRQn" in CMSIS header MK70F12.h.
29 is 45 - 16 and 61 is 45 + 16.
This led me to (my thought) a very unclear documentation of "IRQn" values and the 16 offset.
Seems programmer of µVision Event Viewer window fell in same hole (seems he does "-16" for ISRn). Best regards Juergen.

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