This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Use SDRAM in STM32F429-DISCO, KeilARM 4

Hi Keil.

I have a trouble with using SDRAM. (I'm using STM32F429-DISCO Ev Kit)

I read some question and discussion in forum abt this.

I have a project use SDRAM. But it's not working. Hope some one can help me.

My Keil4 Project Target Option Setting...

---------------------------------------------------------
Read/Only Memory Areas
      ROM1  :
      ROM2  :
      ROM3  :

     On-Chip
v    IROM1  : 0x8000000    0x100000   Startup
     IROM2  :
---------------------------------------------------------
Read/Write Memory Areas
v     RAM1  : 0xD0000000   0x800000
      RAM2  :
      RAM3  :

     On-Chip
v    IRAM1  : 0x20000000   0x30000
v    IRAM2  : 0x10000000   0x10000
---------------------------------------------------------

STM32F42x_System.c
#define DATA_IN_ExtSDRAM Enable.
[ RAM1 : 0xD0000000 0x800000 ] This Option Disable.
Initialize SDRAM OK.
SDRAM Read/Write is Very Well.

But This Option
[ RAM1 : 0xD0000000 0x800000 ] This Option Enable.
I Want SDRAM Use .bss .data Section.

Initialize SDRAM OK.
SDRAM Read/Write is not Working.

My Application is HardFault. (JTAG DEBUG Check)
Dies before the main function call.

I have a project use SDRAM. But it's not working. Hope some one can help me.

thanks.

Parents

0 BOHYUN CHOI over 11 years ago in reply to Westonsupermare Pier

My SDRAM Init Code

#ifdef DATA_IN_ExtSDRAM
/**
  * @brief  Setup the external memory controller.
  *         Called in startup_stm32f4xx.s before jump to main.
  *         This function configures the external SDRAM mounted on STM324x9I_EVAL board
  *         This SDRAM will be used as program data memory (including heap and stack).

 +-------------------+--------------------+--------------------+--------------------+
 | PD0  <-> FMC_D2   | PE0  <-> FMC_NBL0  | PF0  <-> FMC_A0    | PG0  <-> FMC_A10   |
 | PD1  <-> FMC_D3   | PE1  <-> FMC_NBL1  | PF1  <-> FMC_A1    | PG1  <-> FMC_A11   |
 | PD8  <-> FMC_D13  | PE7  <-> FMC_D4    | PF2  <-> FMC_A2    | PG8  <-> FMC_SDCLK |
 | PD9  <-> FMC_D14  | PE8  <-> FMC_D5    | PF3  <-> FMC_A3    | PG15 <-> FMC_NCAS  |
 | PD10 <-> FMC_D15  | PE9  <-> FMC_D6    | PF4  <-> FMC_A4    |--------------------+
 | PD14 <-> FMC_D0   | PE10 <-> FMC_D7    | PF5  <-> FMC_A5    | PB5 <-> FMC_SDCKE1 |
 | PD15 <-> FMC_D1   | PE11 <-> FMC_D8    | PF11 <-> FMC_NRAS  | PB6 <-> FMC_SDNE1  |
 +-------------------| PE12 <-> FMC_D9    | PF12 <-> FMC_A6    | PC0 <-> FMC_SDNWE  |
                     | PE13 <-> FMC_D10   | PF13 <-> FMC_A7    +--------------------+
                     | PE14 <-> FMC_D11   | PF14 <-> FMC_A8    |
                     | PE15 <-> FMC_D12   | PF15 <-> FMC_A9    |
                     +--------------------+--------------------+
  */
//[*]----------------------------------------------------------------------------------------------------------------[*]
void SystemInit_ExtMemCtl(void)
{
    register uint32_t timeout = 0xFFFF;

    FMC_SDRAMInitTypeDef        FMCI;
    FMC_SDRAMTimingInitTypeDef  FMCT;
    FMC_SDRAMCommandTypeDef     FMCC;
    GPIO_InitTypeDef            GPIO;
    GPIO.GPIO_Speed     =       GPIO_Speed_50MHz;                                           //  GPIO_Mode_IN/OUT/AF/AN, GPIO_OType_PP/OD, GPIO_PuPd_NOPULL/UP/DOWN

    RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC  , ENABLE);                                   //  Enable FMC clock
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE);

//  SETGPIO(GPIO, GPIOC,  2, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDCKE0
/   SETGPIO(GPIO, GPIOC,  3, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNE0       0xC000 0000

    SETGPIO(GPIO, GPIOB,  5, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDCKE1
    SETGPIO(GPIO, GPIOB,  6, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNE1       0xD000 0000

    SETGPIO(GPIO, GPIOC,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNWE
    SETGPIO(GPIO, GPIOF, 11, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNRAS
    SETGPIO(GPIO, GPIOG,  8, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDCLK
    SETGPIO(GPIO, GPIOG, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNCAS
    SETGPIO(GPIO, GPIOE,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  NBL0
    SETGPIO(GPIO, GPIOE,  1, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  NBL1

    SETGPIO(GPIO, GPIOD, 14, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D0
    SETGPIO(GPIO, GPIOD, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D1
    SETGPIO(GPIO, GPIOD,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D2
    SETGPIO(GPIO, GPIOD,  1, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D3
    SETGPIO(GPIO, GPIOE,  7, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D4
    SETGPIO(GPIO, GPIOE,  8, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D5
    SETGPIO(GPIO, GPIOE,  9, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D6
    SETGPIO(GPIO, GPIOE, 10, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D7
    SETGPIO(GPIO, GPIOE, 11, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D8
    SETGPIO(GPIO, GPIOE, 12, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D9
    SETGPIO(GPIO, GPIOE, 13, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D10
    SETGPIO(GPIO, GPIOE, 14, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D11
    SETGPIO(GPIO, GPIOE, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D12
    SETGPIO(GPIO, GPIOD,  8, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D13
    SETGPIO(GPIO, GPIOD,  9, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D14
    SETGPIO(GPIO, GPIOD, 10, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D15
    SETGPIO(GPIO, GPIOD, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D13

    SETGPIO(GPIO, GPIOF,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A0
    SETGPIO(GPIO, GPIOF,  1, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A1
    SETGPIO(GPIO, GPIOF,  2, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A2
    SETGPIO(GPIO, GPIOF,  3, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A3
    SETGPIO(GPIO, GPIOF,  4, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A4
    SETGPIO(GPIO, GPIOF,  5, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A5
    SETGPIO(GPIO, GPIOF, 12, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A6
    SETGPIO(GPIO, GPIOF, 13, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A7
    SETGPIO(GPIO, GPIOF, 14, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A8
    SETGPIO(GPIO, GPIOF, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A9
    SETGPIO(GPIO, GPIOG,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A10
    SETGPIO(GPIO, GPIOG,  1, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A11

    SETGPIO(GPIO, GPIOG,  4, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  BA0
    SETGPIO(GPIO, GPIOG,  5, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  BA1

Reply

0 BOHYUN CHOI over 11 years ago in reply to Westonsupermare Pier

My SDRAM Init Code

#ifdef DATA_IN_ExtSDRAM
/**
  * @brief  Setup the external memory controller.
  *         Called in startup_stm32f4xx.s before jump to main.
  *         This function configures the external SDRAM mounted on STM324x9I_EVAL board
  *         This SDRAM will be used as program data memory (including heap and stack).

 +-------------------+--------------------+--------------------+--------------------+
 | PD0  <-> FMC_D2   | PE0  <-> FMC_NBL0  | PF0  <-> FMC_A0    | PG0  <-> FMC_A10   |
 | PD1  <-> FMC_D3   | PE1  <-> FMC_NBL1  | PF1  <-> FMC_A1    | PG1  <-> FMC_A11   |
 | PD8  <-> FMC_D13  | PE7  <-> FMC_D4    | PF2  <-> FMC_A2    | PG8  <-> FMC_SDCLK |
 | PD9  <-> FMC_D14  | PE8  <-> FMC_D5    | PF3  <-> FMC_A3    | PG15 <-> FMC_NCAS  |
 | PD10 <-> FMC_D15  | PE9  <-> FMC_D6    | PF4  <-> FMC_A4    |--------------------+
 | PD14 <-> FMC_D0   | PE10 <-> FMC_D7    | PF5  <-> FMC_A5    | PB5 <-> FMC_SDCKE1 |
 | PD15 <-> FMC_D1   | PE11 <-> FMC_D8    | PF11 <-> FMC_NRAS  | PB6 <-> FMC_SDNE1  |
 +-------------------| PE12 <-> FMC_D9    | PF12 <-> FMC_A6    | PC0 <-> FMC_SDNWE  |
                     | PE13 <-> FMC_D10   | PF13 <-> FMC_A7    +--------------------+
                     | PE14 <-> FMC_D11   | PF14 <-> FMC_A8    |
                     | PE15 <-> FMC_D12   | PF15 <-> FMC_A9    |
                     +--------------------+--------------------+
  */
//[*]----------------------------------------------------------------------------------------------------------------[*]
void SystemInit_ExtMemCtl(void)
{
    register uint32_t timeout = 0xFFFF;

    FMC_SDRAMInitTypeDef        FMCI;
    FMC_SDRAMTimingInitTypeDef  FMCT;
    FMC_SDRAMCommandTypeDef     FMCC;
    GPIO_InitTypeDef            GPIO;
    GPIO.GPIO_Speed     =       GPIO_Speed_50MHz;                                           //  GPIO_Mode_IN/OUT/AF/AN, GPIO_OType_PP/OD, GPIO_PuPd_NOPULL/UP/DOWN

    RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC  , ENABLE);                                   //  Enable FMC clock
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE);

//  SETGPIO(GPIO, GPIOC,  2, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDCKE0
/   SETGPIO(GPIO, GPIOC,  3, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNE0       0xC000 0000

    SETGPIO(GPIO, GPIOB,  5, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDCKE1
    SETGPIO(GPIO, GPIOB,  6, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNE1       0xD000 0000

    SETGPIO(GPIO, GPIOC,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNWE
    SETGPIO(GPIO, GPIOF, 11, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNRAS
    SETGPIO(GPIO, GPIOG,  8, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDCLK
    SETGPIO(GPIO, GPIOG, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  SDNCAS
    SETGPIO(GPIO, GPIOE,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  NBL0
    SETGPIO(GPIO, GPIOE,  1, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  NBL1

    SETGPIO(GPIO, GPIOD, 14, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D0
    SETGPIO(GPIO, GPIOD, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D1
    SETGPIO(GPIO, GPIOD,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D2
    SETGPIO(GPIO, GPIOD,  1, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D3
    SETGPIO(GPIO, GPIOE,  7, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D4
    SETGPIO(GPIO, GPIOE,  8, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D5
    SETGPIO(GPIO, GPIOE,  9, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D6
    SETGPIO(GPIO, GPIOE, 10, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D7
    SETGPIO(GPIO, GPIOE, 11, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D8
    SETGPIO(GPIO, GPIOE, 12, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D9
    SETGPIO(GPIO, GPIOE, 13, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D10
    SETGPIO(GPIO, GPIOE, 14, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D11
    SETGPIO(GPIO, GPIOE, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D12
    SETGPIO(GPIO, GPIOD,  8, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D13
    SETGPIO(GPIO, GPIOD,  9, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D14
    SETGPIO(GPIO, GPIOD, 10, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D15
    SETGPIO(GPIO, GPIOD, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  D13

    SETGPIO(GPIO, GPIOF,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A0
    SETGPIO(GPIO, GPIOF,  1, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A1
    SETGPIO(GPIO, GPIOF,  2, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A2
    SETGPIO(GPIO, GPIOF,  3, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A3
    SETGPIO(GPIO, GPIOF,  4, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A4
    SETGPIO(GPIO, GPIOF,  5, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A5
    SETGPIO(GPIO, GPIOF, 12, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A6
    SETGPIO(GPIO, GPIOF, 13, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A7
    SETGPIO(GPIO, GPIOF, 14, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A8
    SETGPIO(GPIO, GPIOF, 15, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A9
    SETGPIO(GPIO, GPIOG,  0, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A10
    SETGPIO(GPIO, GPIOG,  1, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  A11

    SETGPIO(GPIO, GPIOG,  4, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  BA0
    SETGPIO(GPIO, GPIOG,  5, GPIO_Mode_AF, GPIO_OType_PP, GPIO_PuPd_NOPULL, GPIO_AF_FMC);   //  BA1

Children

0 BOHYUN CHOI over 11 years ago in reply to BOHYUN CHOI

    //  FMC SDRAM device initialization sequence
    //  Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2)
    //  TMRD : 2 Clock cycles

    FMCT.FMC_LoadToActiveDelay      = 0x02;                         //  2   1 clock cycle = 1 / 84MHz = 11.90ns
    FMCT.FMC_ExitSelfRefreshDelay   = 0x06;                         //  6   TXSR: min=70ns  (  6x11.90ns)
    FMCT.FMC_SelfRefreshTime        = 0x04;                         //  4   TRAS: min=42ns  (  4x11.90ns) max = 120k (ns)
    FMCT.FMC_RowCycleDelay          = 0x06;                         //  6   TRC:  min=70ns  (  7x11.90ns)
    FMCT.FMC_WriteRecoveryTime      = 0x02;                         //  2   TWR:  min=1+7ns (1+1x11.90ns)
    FMCT.FMC_RPDelay                = 0x02;                         //  2   TRP:  20ns      (  2x11.90ns)
    FMCT.FMC_RCDDelay               = 0x02;                         //  2   TRCD: 20ns      (  2x11.90ns)

    FMCI.FMC_Bank                   = FMC_Bank2_SDRAM;              //  FMC SDRAM control configuration
    FMCI.FMC_ColumnBitsNumber       = FMC_ColumnBits_Number_8b;     //  Row addressing   : [ 7:0]
    FMCI.FMC_RowBitsNumber          = FMC_RowBits_Number_12b;       //  Column addressing: [11:0]
    FMCI.FMC_SDMemoryDataWidth      = FMC_SDMemory_Width_16b;
    FMCI.FMC_InternalBankNumber     = FMC_InternalBank_Number_4;
    FMCI.FMC_CASLatency             = FMC_CAS_Latency_3;            //  CL: Cas Latency = 3 clock cycles
    FMCI.FMC_WriteProtection        = FMC_Write_Protection_Disable;
    FMCI.FMC_SDClockPeriod          = FMC_SDClock_Period_2;
    FMCI.FMC_ReadBurst              = FMC_Read_Burst_Disable;
    FMCI.FMC_ReadPipeDelay          = FMC_ReadPipe_Delay_1;
    FMCI.FMC_SDRAMTimingStruct      = &FMCT;
    FMC_SDRAMInit(&FMCI);                                           //  FMC SDRAM bank initialization

    //  Configure a clock configuration enable command
    FMCC.FMC_CommandMode            = FMC_Command_Mode_CLK_Enabled;
    FMCC.FMC_CommandTarget          = FMC_Command_Target_bank2;
    FMCC.FMC_AutoRefreshNumber      = 1;
    FMCC.FMC_ModeRegisterDefinition = 0;
    while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET);
    FMC_SDRAMCmdConfig(&FMCC);

    for(timeout = 0x00; timeout < 0xD0000; timeout++) {}

    //  Configure a PALL (precharge all) command
    FMCC.FMC_CommandMode            = FMC_Command_Mode_PALL;
    FMCC.FMC_CommandTarget          = FMC_Command_Target_bank2;
    FMCC.FMC_AutoRefreshNumber      = 1;
    FMCC.FMC_ModeRegisterDefinition = 0;
    while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy));
    FMC_SDRAMCmdConfig(&FMCC);

    //  Configure a Auto-Refresh command
    FMCC.FMC_CommandMode            = FMC_Command_Mode_AutoRefresh;
    FMCC.FMC_CommandTarget          = FMC_Command_Target_bank2;
    FMCC.FMC_AutoRefreshNumber      = 4;
    FMCC.FMC_ModeRegisterDefinition = 0;
    while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy));
    FMC_SDRAMCmdConfig(&FMCC);

    //  Configure a load Mode register command
    #define SDRAM_BURST_LENGTH_1                ((uint16_t)0x0000)
    #define SDRAM_BURST_LENGTH_2                ((uint16_t)0x0001)
    #define SDRAM_BURST_LENGTH_4                ((uint16_t)0x0002)
    #define SDRAM_BURST_LENGTH_8                ((uint16_t)0x0004)
    #define SDRAM_BURST_TYPE_SEQUENTIAL         ((uint16_t)0x0000)
    #define SDRAM_BURST_TYPE_INTERLEAVED        ((uint16_t)0x0008)
    #define SDRAM_CAS_LATENCY_2                 ((uint16_t)0x0020)
    #define SDRAM_CAS_LATENCY_3                 ((uint16_t)0x0030)
    #define SDRAM_OPERATING_MODE_STANDARD       ((uint16_t)0x0000)
    #define SDRAM_WRITEBURST_MODE_PROGRAMMED    ((uint16_t)0x0000)
    #define SDRAM_WRITEBURST_MODE_SINGLE        ((uint16_t)0x0200)

    #define SDRAM_MODEREG                       (SDRAM_BURST_LENGTH_2           |   \ 
                                                 SDRAM_BURST_TYPE_SEQUENTIAL    |   \ 
                                                 SDRAM_CAS_LATENCY_3            |   \ 
                                                 SDRAM_OPERATING_MODE_STANDARD  |   \ 
                                                 SDRAM_WRITEBURST_MODE_SINGLE)

    FMCC.FMC_CommandMode            = FMC_Command_Mode_LoadMode;
    FMCC.FMC_CommandTarget          = FMC_Command_Target_bank2;
    FMCC.FMC_AutoRefreshNumber      = 1;
    FMCC.FMC_ModeRegisterDefinition = SDRAM_MODEREG;
    while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy));
    FMC_SDRAMCmdConfig(&FMCC);

    //  Set the refresh rate counter
    //  (7.81 us x Freq) - 20 = (7.81 * 84MHz) - 20 = 683
    //  Set the device refresh counter

//  FMC_SetRefreshCount(1386);
    FMC_SetRefreshCount(683);
    while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET);
}

#endif /* DATA_IN_ExtSDRAM */

0 Westonsupermare Pier over 11 years ago in reply to BOHYUN CHOI

Make sure your initial stack is in regular SRAM
Cancel
Vote up 0 Vote down

Cancel