Hi Keil.
I have a trouble with using SDRAM. (I'm using STM32F429-DISCO Ev Kit) I read some question and discussion in forum abt this.
I have a project use SDRAM. But it's not working. Hope some one can help me. My Keil4 Project Target Option Setting...
--------------------------------------------------------- Read/Only Memory Areas ROM1 : ROM2 : ROM3 : On-Chip v IROM1 : 0x8000000 0x100000 Startup IROM2 : --------------------------------------------------------- Read/Write Memory Areas v RAM1 : 0xD0000000 0x800000 RAM2 : RAM3 : On-Chip v IRAM1 : 0x20000000 0x30000 v IRAM2 : 0x10000000 0x10000 ---------------------------------------------------------
STM32F42x_System.c #define DATA_IN_ExtSDRAM Enable. [ RAM1 : 0xD0000000 0x800000 ] This Option Disable. Initialize SDRAM OK. SDRAM Read/Write is Very Well. But This Option [ RAM1 : 0xD0000000 0x800000 ] This Option Enable. I Want SDRAM Use .bss .data Section. Initialize SDRAM OK. SDRAM Read/Write is not Working. My Application is HardFault. (JTAG DEBUG Check) Dies before the main function call. I have a project use SDRAM. But it's not working. Hope some one can help me. thanks.
// FMC SDRAM device initialization sequence // Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) // TMRD : 2 Clock cycles FMCT.FMC_LoadToActiveDelay = 0x02; // 2 1 clock cycle = 1 / 84MHz = 11.90ns FMCT.FMC_ExitSelfRefreshDelay = 0x06; // 6 TXSR: min=70ns ( 6x11.90ns) FMCT.FMC_SelfRefreshTime = 0x04; // 4 TRAS: min=42ns ( 4x11.90ns) max = 120k (ns) FMCT.FMC_RowCycleDelay = 0x06; // 6 TRC: min=70ns ( 7x11.90ns) FMCT.FMC_WriteRecoveryTime = 0x02; // 2 TWR: min=1+7ns (1+1x11.90ns) FMCT.FMC_RPDelay = 0x02; // 2 TRP: 20ns ( 2x11.90ns) FMCT.FMC_RCDDelay = 0x02; // 2 TRCD: 20ns ( 2x11.90ns) FMCI.FMC_Bank = FMC_Bank2_SDRAM; // FMC SDRAM control configuration FMCI.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; // Row addressing : [ 7:0] FMCI.FMC_RowBitsNumber = FMC_RowBits_Number_12b; // Column addressing: [11:0] FMCI.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; FMCI.FMC_InternalBankNumber = FMC_InternalBank_Number_4; FMCI.FMC_CASLatency = FMC_CAS_Latency_3; // CL: Cas Latency = 3 clock cycles FMCI.FMC_WriteProtection = FMC_Write_Protection_Disable; FMCI.FMC_SDClockPeriod = FMC_SDClock_Period_2; FMCI.FMC_ReadBurst = FMC_Read_Burst_Disable; FMCI.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; FMCI.FMC_SDRAMTimingStruct = &FMCT; FMC_SDRAMInit(&FMCI); // FMC SDRAM bank initialization // Configure a clock configuration enable command FMCC.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; FMCC.FMC_CommandTarget = FMC_Command_Target_bank2; FMCC.FMC_AutoRefreshNumber = 1; FMCC.FMC_ModeRegisterDefinition = 0; while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET); FMC_SDRAMCmdConfig(&FMCC); for(timeout = 0x00; timeout < 0xD0000; timeout++) {} // Configure a PALL (precharge all) command FMCC.FMC_CommandMode = FMC_Command_Mode_PALL; FMCC.FMC_CommandTarget = FMC_Command_Target_bank2; FMCC.FMC_AutoRefreshNumber = 1; FMCC.FMC_ModeRegisterDefinition = 0; while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy)); FMC_SDRAMCmdConfig(&FMCC); // Configure a Auto-Refresh command FMCC.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; FMCC.FMC_CommandTarget = FMC_Command_Target_bank2; FMCC.FMC_AutoRefreshNumber = 4; FMCC.FMC_ModeRegisterDefinition = 0; while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy)); FMC_SDRAMCmdConfig(&FMCC); // Configure a load Mode register command #define SDRAM_BURST_LENGTH_1 ((uint16_t)0x0000) #define SDRAM_BURST_LENGTH_2 ((uint16_t)0x0001) #define SDRAM_BURST_LENGTH_4 ((uint16_t)0x0002) #define SDRAM_BURST_LENGTH_8 ((uint16_t)0x0004) #define SDRAM_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) #define SDRAM_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) #define SDRAM_CAS_LATENCY_2 ((uint16_t)0x0020) #define SDRAM_CAS_LATENCY_3 ((uint16_t)0x0030) #define SDRAM_OPERATING_MODE_STANDARD ((uint16_t)0x0000) #define SDRAM_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) #define SDRAM_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) #define SDRAM_MODEREG (SDRAM_BURST_LENGTH_2 | \ SDRAM_BURST_TYPE_SEQUENTIAL | \ SDRAM_CAS_LATENCY_3 | \ SDRAM_OPERATING_MODE_STANDARD | \ SDRAM_WRITEBURST_MODE_SINGLE) FMCC.FMC_CommandMode = FMC_Command_Mode_LoadMode; FMCC.FMC_CommandTarget = FMC_Command_Target_bank2; FMCC.FMC_AutoRefreshNumber = 1; FMCC.FMC_ModeRegisterDefinition = SDRAM_MODEREG; while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy)); FMC_SDRAMCmdConfig(&FMCC); // Set the refresh rate counter // (7.81 us x Freq) - 20 = (7.81 * 84MHz) - 20 = 683 // Set the device refresh counter // FMC_SetRefreshCount(1386); FMC_SetRefreshCount(683); while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET); } #endif /* DATA_IN_ExtSDRAM */
Make sure your initial stack is in regular SRAM