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Hello everyone,
We're about to begin a project with NXP's LPC4350 chip, which features the following memory configuration:
- 128kB Local SRAM - 72kB Local SRAM - SPIFI - 32kB AHB SRAM - 16kB AHB SRAM - External Memory Controller (SRAM, SDRAM)
The LPC4350 features a dual-core M4 and M0 clocked at up to 204MHz.
Instinctively we wish to use the 128 and 72kB memory banks for the M4 Data and Instruction buses, as these are in the accessible memory range, whilst AHB elements run only on the system bus.
However, we wish to offload MDK Ethernet functionality to the M0 and, with a little extra logic, the 32 and 16kB memory spaces are looking rather insufficient and so we're finding ourselves turning to external memory for an answer.
Available to us are SPIFI and SRAM (which can be accessed via the M4's D and I bus) and SDRAM, which, whilst it makes no difference to the M0, can be accessed only by the M4's System Bus.
We're curious to find out if anyone has had any experience with this chip and what configurations have/should provide the best performance? Likewise, we'd very much like to hear the opinions of anyone who has had similar challenges before and very much welcome and appreciate any input.
Many thanks
Hi Alistair,
You can use the EMC from both the M4 or the M0 so your original plan to offload Ethernet to the M0 and keep buffers in memory would work. This is described in the User's Manual in Figure 8, the LPC43xx AHB multilayer matrix connections which shows that the EMC is connected to both the M4 and the M0. External SDRAM is usually quicker than external SRAM on this part because of bursting. Ideally, the most performance critical code (probably M4 DSP code) would be placed in internal SRAM for best performance.
Not knowing what else your system needs to do, here is what I would do for best performance for the M4: external SDRAM- M0 Ethernet stack code + buffers internal SRAM block 1- M4 data + stack internal SRAM block 2- M4 code internal AHB SRAM- M0 stack
Another option is to look at the flash version of this part which has up to 1 MB of on-chip flash which is almost as fast as the on-chip SRAM and would give more room for high-speed code storage.
-Dave
Thank you very much for taking the time to reply.
I've since also spoken to NXP who've agreed with your take on the matter and who also noted that QSPI is faster than both SDRAM and SRAM due to the use of an accelerator module, though is no good for writing - but as it runs on a separate channel on the AHB bus so can be great for storing static code.