Hi I have simple question about lpc1788:
*. what's the maximum bit rate of LPC1788 SSP?
maybe it's duplicated question but I need to be sure because I wanna buy and design new board and SSP bit rate is critical for me
more than 30Mbps is OK for me.
thanks in advance
The CPSR divider needs to have a min value of 8 so with 120MHZ core clock you can get a max of 15MHz for the SSP clock.
Alex
The theoretical value differs greatly from the maximum allowed by real-world hardware. Issues with trace length, buffers along the way of the signals etc. might limits signal propogation. I have just finished a simulator project that uses SSP1 of a LPC1768 at 100 MHz but the SSP bus is limited to 12.5 MHz.
A max frequency limit may apply because of external factors like the PCB tracks you mention but you say that you have used a LPC1768 at 100 MHz but the SSP bus is limited to 12.5 MHz.
Why do you say limited, this is the max frequency based on specs for a core operating with 100MHZ, 100MHz/8=12.5MHz for the SSP clock
In this case it is; I was trying to demonstrate the necessity to consider factors other than the software itself.
Hi in datasheet mentioned this number should be between 2-245 and even
where is "8"?
there is no any other fast serial protocol for lpc1788 about 30mbps or more?
I should connect it to spartan3 FPGA and this speed is awful. I don't have enough GPIO in FPGA and MCU and I must to transfer data between those, about 4MBps.
thanks a lot
You are absolutely right , the minimum divider of 8 is the case for the SPI peripheral and not the SSP.
Note that a value of 255 is not possible because only even numbers should be used which means up to 254.
;-( So...!!! which one is correct? minimum=8 or 2
SPI or SSP can transmit up to what?
SPI can transmit up to core_clock/8 and SSP core_clock/2.
you mean LPC1788 on SSP can transmit up to 60Mbps without any limitation.
I knew I should observe a lot of things to make such a high speed connection about PCB design and etc but is it possible to gain more than 30mbps or IO pins can't toggle with such a speed (rising time and falling time or else doesn't limit these signals).
would you please do me a favor: config SSP to maximum speed and with Oscilloscope check it whether the signals are correct or have Distortion.
because I should select a powerful MCU with high speed SPI or SSP and if LPC1788 can satisfy me then I can buy it.
I'll appreciate you.
thanks
Let me rephrase, according to the datasheet the max SSP clock is core_clock/2.
Even if it is possible to get such a rate externally it would not leave much cpu time to do anything that send spi.
Let me also add that in the following link it says ics.nxp.com/.../
Q : What is the maximum SSP speed on the LPC17xx? A : The maximum SSP speed (in master mode) is pclk/2. The maximum clock (CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral clock (PCLK) can be equal to CCLK, the maximum SSP rate (master mode) will be 50 Mbit/sec (100MHz/2). In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the SSP peripheral clock (selected in peripheral clock selection register). The content of the SSPnCPSR register is not relevant. So, the maximum SSP speed (in slave mode) will be 8Mbit/sec.
thanks Alex , you are so fast to response that's so good information
thanks thanks thanks