Anyone can help me with this? i cant get any output.
-- pwm1generator.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PWMgenerator1 is generic( N: natural := 16; Max: natural := 65536); Port ( Clk : in STD_LOGIC; PCM : in STD_LOGIC_VECTOR (15 downto 0); PWM : out STD_LOGIC ); -- or SD end PWMgenerator1;
ARCHITECTURE Behavioral of PWMgenerator1 is signal PWM_Count: STD_LOGIC_VECTOR (N-1 downto 0) := (others=>'0');
signal Scaled_clk: STD_LOGIC; begin
process( Clk) variable Scalex: integer; variable Count: integer range 0 to 50000001 := 0; begin if rising_edge(Clk)then if Count>=Scalex then Scaled_clk <= '1'; Count := 0; else Scaled_clk <= '0'; Count := Count+1; end if; end if; end process;
PWM_Generator: process( Clk, PWM_Count, PCM) begin if rising_edge(Clk) then if Scaled_Clk='1' then if PWM_Count<Max-1 then PWM_Count <= PWM_Count+1; else PWM_Count <= (others => '0'); end if; end if; end if;
if PWM_Count<PCM then PWM <= '1'; else PWM <= '0'; end if; end process PWM_Generator;
end Behavioral;
AARON TAN,
Your original VHDL code... (cleaned up a bit)
-- pwm1generator.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PWMgenerator1 is generic ( N: natural := 16; Max: natural := 65536 ); Port ( Clk : in STD_LOGIC; PCM : in STD_LOGIC_VECTOR (15 downto 0); PWM : out STD_LOGIC -- or SD ); end PWMgenerator1; ARCHITECTURE Behavioral of PWMgenerator1 is signal PWM_Count: STD_LOGIC_VECTOR( N-1 downto 0 ) := (others => '0'); signal Scaled_clk: STD_LOGIC; begin process( Clk ) variable Scalex: integer; variable Count: integer range 0 to 50000001 := 0; --------------------------------------------------------------------- -- -- -- Pre-scaler for clocking down the Clk to Scaled_clk -- -- -- --------------------------------------------------------------------- begin if rising_edge( Clk ) then if Count >= Scalex then Scaled_clk <= '1'; Count := 0; else Scaled_clk <= '0'; Count := Count + 1; end if; end if; end process; --------------------------------------------------------------------- -- -- -- Compare the PWM_Count with the 'PCM' value to toggle 'PWM' -- -- -- --------------------------------------------------------------------- PWM_Generator: process( Clk, PWM_Count, PCM ) begin ----------------------------------------------------------------- -- Check to see if we bump the PWM_Count, reset if > Max -- ----------------------------------------------------------------- if rising_edge( Clk ) then -- synchronize with Clk if Scaled_Clk = '1' then -- When '1' bump PWM_Count-- ERROR -- ERROR if PWM_Count < Max-1 then -- ERROR PWM_Count <= PWM_Count + 1; -- Bump PWM_Count else PWM_Count <= (others => '0'); -- Reset PWM_Count end if; end if; end if; ----------------------------------------------------------------- -- THE PWM ACTION -- ----------------------------------------------------------------- -- PWM = 1 if PWM_Count < PCM, otherwise PWM = 0 -- ----------------------------------------------------------------- if PWM_Count < PCM then PWM <= '1'; else PWM <= '0'; end if; end process PWM_Generator; end Behavioral;
When the test for Scaled_Clk = '1' occurs, the PWM_Count value shall count up rapidly. Each Clk [rising] edge will cause PWM_Count bumps in bursts.
You did not reduce the clock frequency as you think you have. All you did was turn on the ability of the PWM_Count to start counting the Clk [rising] edge at that clock frequency, and then stop its counting when 'Scaled_Clk' goes to '0'.
When Scaled_Clk is '1', the PWM_Count will count on every Clk pulse, and thus will reach its maximum rapidly and reset when PWM_Count > Max-1.
Also, you have two different cases of 'Scaled_Clk' and 'Scaled_clk' (You should be consistant)
And you should use parentheses as often as possible:
if( Scaled_Clk = '1' ) then if( PWM_Count < Max-1 ) then
--Cpt. Vince Foster 2nd Cannon Place Fort Marcy Park, VA