Anyone can help me with this? i cant get any output.
-- pwm1generator.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PWMgenerator1 is generic( N: natural := 16; Max: natural := 65536); Port ( Clk : in STD_LOGIC; PCM : in STD_LOGIC_VECTOR (15 downto 0); PWM : out STD_LOGIC ); -- or SD end PWMgenerator1;
ARCHITECTURE Behavioral of PWMgenerator1 is signal PWM_Count: STD_LOGIC_VECTOR (N-1 downto 0) := (others=>'0');
signal Scaled_clk: STD_LOGIC; begin
process( Clk) variable Scalex: integer; variable Count: integer range 0 to 50000001 := 0; begin if rising_edge(Clk)then if Count>=Scalex then Scaled_clk <= '1'; Count := 0; else Scaled_clk <= '0'; Count := Count+1; end if; end if; end process;
PWM_Generator: process( Clk, PWM_Count, PCM) begin if rising_edge(Clk) then if Scaled_Clk='1' then if PWM_Count<Max-1 then PWM_Count <= PWM_Count+1; else PWM_Count <= (others => '0'); end if; end if; end if;
if PWM_Count<PCM then PWM <= '1'; else PWM <= '0'; end if; end process PWM_Generator;
end Behavioral;