Hello, I am stuck with handling interrupts on lpc3180 uC.I have the following interrupt routine:
void IRQ_Handler (void) __irq { MSTIM_INT = MSTIM_INT | 2; PIO_OUTP_SET | = 4; MSTIM_CTRL = MSTIM_CTRL | 1; }
and the following modifications done to the startup code (PHYTEC_LPC3000.s) :
;IRQ_Handler B IRQ_Handler ;(commented) IMPORT IRQ_Handler ;(added)
The problem is that the code does not compile, I get the following error description:
PHYTEC_LPC3000.s(666): error: A1163E: Unknown opcode IRQ_Handler , expecting opcode or Macro PHYTEC_LPC3000.s: 666 00000058 IMPORT IRQ_Handler ; Enable IRQ HANDLER
Could someone please give a hint of what could possibly cause the compilation failure and how should I modify the code so, that it would become acceptable? Thanks in advance!
Smells like an excessive space in the line that causes the error. Align it with the ones above it to be sure.
Just tried, does not change anything, I am afraid there is a more fundamental problem (some definition is missing or something like that), but, being quite novice to ARM programming, I have no idea, which one :(((
Tamir probably has a strong desire to assist you.
Burp.
Look, buddy, I don't feel like replying to you but I will deviate from my general guideline not to confront assholes and do so once - and never again: 1. Why are you hiding behind a monikers? Have an identity complex? 2. I'm not related to the poster above. 3. I don't care what you say, think, do or whatever so spare me and the rest - they are even less interested. 4. There are doctors that treat people like you. You should get yourself tested/checked/admitted/put away. 5. Burp.
If that is the case, then it a simple matter of mistaken identity and I really should offer you my sincerest appologies.
In LPC3000.s
Vectors LDR PC,Reset_Addr LDR PC,Undef_Addr LDR PC,SWI_Addr LDR PC,PAbt_Addr LDR PC,DAbt_Addr IF :DEF:__EVAL DCD 0x4000 ELSE DCD ||Image$$ER_ROM1$$RO$$Length||+\ ||Image$$RW_RAM1$$RW$$Length|| ENDIF LDR PC,IRQ_Addr LDR PC,FIQ_Addr Reset_Addr DCD Reset_Handler Undef_Addr DCD Undef_Handler SWI_Addr DCD SWI_Handler PAbt_Addr DCD PAbt_Handler DAbt_Addr DCD DAbt_Handler DCD 0 ; Reserved Address IRQ_Addr DCD IRQ_Handler FIQ_Addr DCD FIQ_Handler Undef_Handler B Undef_Handler SWI_Handler B SWI_Handler PAbt_Handler B PAbt_Handler DAbt_Handler B DAbt_Handler IRQ_Handler B IRQ_Handler FIQ_Handler B FIQ_Handler
So, I think/guess that, only modifying [IRQ_Handler B IRQ_Handler] is not enough.
Sorry for my mistake. Please ignore my previous post, it is wrong.
I tried this, it can be compiled.
Undef_Handler B Undef_Handler SWI_Handler B SWI_Handler PAbt_Handler B PAbt_Handler DAbt_Handler B DAbt_Handler ;IRQ_Handler B IRQ_Handler IMPORT IRQ_Handler FIQ_Handler B FIQ_Handler
Many thanks! It really works, I have to admit, my suggestion, that the reason of failure cannot be connected with alignment of the lines was totally wrong.From now I will keep this in mind.
"Smells like an excessive space in the line that causes the error. Align it with the ones above it to be sure."
Can't remember ever writing this, but glad my advice helped.
I tried this, it can NOT be compiled.
And the error message is: LPC3000.s(664): error: A1163E: Unknown opcode IRQ_Handler , expecting opcode or Macro
My Lag.
Got the code compiled, but the program gets stuck. When the first interrupt comes, it fails jumping to interrupt service routine.
What does it do when the first interrupt comes? Where does it go? Can you show how your interrupt table looks now?
Just found out, that after deleting the excessive line in the vector table code it actually did work OK, it is just my poor debugging skills and extremely bad mood, that prevented me from realising that, so, I beg your pardon for wasting your time! And the working variant of the interrupt vector table code is as follows:
Vectors LDR PC,Reset_Addr LDR PC,Undef_Addr LDR PC,SWI_Addr LDR PC,PAbt_Addr LDR PC,DAbt_Addr DCD ||Image$$ER_IROM1$$RO$$Length|| + ||Image$$RW_IRAM1$$RW$$Length|| DCD 0x4000 ;PHYTEC comment: This hard codes the size ;that the secondary bootloader uses to copy ;binary software to SDRAM. LDR PC,IRQ_Addr LDR PC,FIQ_Addr Reset_Addr DCD Reset_Handler Undef_Addr DCD Undef_Handler SWI_Addr DCD SWI_Handler PAbt_Addr DCD PAbt_Handler DAbt_Addr DCD DAbt_Handler DCD 0 ; Reserved Address IRQ_Addr DCD IRQ_Handler FIQ_Addr DCD FIQ_Handler Undef_Handler B Undef_Handler SWI_Handler B SWI_Handler PAbt_Handler B PAbt_Handler DAbt_Handler B DAbt_Handler ;IRQ_Handler B IRQ_Handler FIQ_Handler B FIQ_Handler IMPORT IRQ_Handler
Once again, excuse me for wrong information and thanks to everyone, who helped to solve the problem!