LPC3250 HSUART HELP

Just now i was able to send. Now problum with receiving n Not able to receive what i am typing

When you read to check the status of the receive FIFO, you are removing a (potentially) pending character from the FIFO.

So your receive code would be better as something like:

unsigned char HSUART1_receivedata(void)
{
  unsigned int gch;

  // Wait for character to become available

  do
  {
    gch = HSU1_RX;
  } while((gch&0x0100)==0x0100);

  // Return the character now read, with FIFO status removed

  return((unsigned char)(gch&0xFF));
}

(I'll leave you to tidy it up!)

Thank You for reply.
I just received on other logic.
But i'll try this one also.

Thanks

Hi Thanks for your help regarding UART. Now i have one more problem. I'm trying to receive the data using trigger levels. But from the first byte interrupt coming. As per the datasheet the interrupt has to come after reaching the trigger level only. But i'm getting interrupt for single character.

here i am attaching the configuration. Please help me.

      U6LCR=0x83;//DLAB enable,odd parity,disble break transmission,1 stop bit,8 bit character length
U6CLK =0x00000101;                      //x=1,y=1..115200
U6DLL=0x07;                             //115200 baud rate
U6DLM=0x00;
U6LCR=0x03;     //DLAB Disable,odd parity,disble break transmission,1 stop bit,8 bit character length
U6IER           |=0x03;                         // Enable Uart6 Rx & Tx interrupt
U6FCR            =0x1F;

Thanks
eswar

You don't mention the frequency at which you are sending characters to the UART.

It would be typical for the UART with FIFOs enabled to generate an interrupt when:

1 - The FIFO trigger point has been reached
2 - If something is in the FIFO, but no further character has been received for 'a period'

So, if you only send one character (or send multiple characters with a relatively large delay between them), you should expect to see an interrupt for each character.

i am sending with 115200 baud rate. char time outCTI interrupt is coming. my requirement is i have to receive 4 bytes as burst and reply with some bytes and again read 8 bytes to start my process. because of the UART6 which i am using don't support DMA to read and send burst i have to enable FIFO for trigger levels. why interrupt coming for each character. How to configure for trigger level.

If you're getting a timeout interrupt, then the characters are coming in with a (relatively large) delay somewhere.

Getting an interrupt like this is useful and you should probably cope with it anyway. Consider what would happen if one of your 4 bytes 'goes missing' (which is not unheard of when using serial communication). You might only receive 3 of your 4 bytes and you will potentially be waiting forever for the 4th byte. So you should implement some sort of timeout check anyway.

It looks like you've got a relatively small amount of communication, so it may be simpler to buffer up characters into a local store as you receive them. Then, it won't matter whether you receive a single interrupt when the FIFO trigger is reached or when you have accumulated your data from a series of interrupts.

Have you actually studied the documentation for the character timeout interrupt, CTI?

I don't know this chip specifically but, as IB Shy says, what you describe sounds like perfectly normal behaviour - exactly as should be expected!

"How to configure for trigger level"

It's probably not the trigger level that you need to look at - are there any options to configure the timeout for the CTI?

But, as IB Shy says, your application really needs to cope with both scenarios...

If you want to ensure that you don't get a character timeout then, obviously, you need to ensure that the time between characters never exceeds - and can never exceed - the timeout value!

If you cannot absolutely guarantee that (as, it seems, you can't) then your application obviously must cope with the possibility of the timeout occurring!

Hi Now i configured for 9600 baud rate. and i sent a text file through hyper terminal. Now i got RDA interrupt but still i got that interrupt for every byte.( which means for each byte program entering into interrupt not for 16 bytes )But expected result is it must be trigger after 16 bytes only (like DMA it has to behave). and one more issue How to read data from buffer if i configured for 16bytes. My doubt is if i read data from buffer after interrupt comes last byte only will display. what abt rest of 15 bytes.

"My doubt is if i read data from buffer after interrupt comes last byte only will display."

Unless the FIFO overruns, you would read the data bytes from the FIFO and you would get the data bytes in the order in which they arrived.

"But expected result is it must be trigger after 16 bytes only ..."

So ... accumulate the characters as they arrive (with your interrupt) into a local store. When you have accumulated your 16 bytes, you can trigger your next action. As I said before, it does not then matter whether you then get an interrupt for one character or a few characters.

You do not want to get an interrupt after 16 characters in the FIFO, unless the FIFO is larger than 16 characters. There are two reasons for a receive FIFO:
- less CPU load by picking up multiple characters each time you get into the ISR.
- support for larger latencies without dropping characters - but that requires that the interrupt gets trigged while the FIFO still has room for more characters.

But many protocols have messages that are way larger than the size of the receive FIFO, requiring the ISR to move the received data to an intermediary buffer until a full message has been received and can be processed.

i want interrupt for trigger level only. if i use DMA i can put less load on CPU. But the UART which i configured is not support DMA on LPC3250(UART6). So i want to use trigger levels for my application. So that if interrupt comes for the trigger level then it will be less load for CPU. Now i am getting interrupt for every character which giving some work for the CPU. i don't want to give job for CPU on this serial port as other processing was running. So please give me solution.

Then you need to ensure that the times between characters can never exceed the inter-character timeout!

Have you actually checked yet whether the inter-character timeout is configurable?

"it will be less load for CPU"

If the incoming characters are so widely spaced that you are getting inter-character timeouts, then this is hardly going to be a major load on the CPU - is it?!

Hi

Thanks for earlier support. I'm facing one more issue on GPDMA. I was unable to generate interrupt on DMA.
1.I configured DMA Channel 0 for UART2 for 4 bytes trigger. But unable to get.

2.What that channel linked list register will do?

I have studied the data sheet. But unable to get these things.

Please help me

Here i'm attaching the GPDMA configuration what i did.

GPDMA_SOFT_BREQ |=0x00000100;           // HSUART 2 TX  Selected
        GPDMA_CH0_SRC    =HSU2_RX;      // Selecting Source address
        GPDMA_CH0_DEST   =(unsigned long)&Rx_Buffer_485[0];
        GPDMA_CH0_LLI    =0x00000000;
        GPDMA_CH0_CTRL   = 0x88009001;          // Terminal count interrupt and
                                                //transfer size 4byts(8bits wide)
        GPDMA_CH0_CFG    |=0x00001008;          // Peripheral to memory trnasaction
        GPDMA_CONFIG     |=0x00000001;          // Enable DMA Controller

Thanks
Eswar