another newbie question.
I have a piece of code that I am porting from PICC. In PICC, you can make reference to specific pins ("#define sclk GPIO5" for example), and in your code, you can write to sclk to change the pin output on GPOI5. This makes porting code or changing pin layout so much easier as you can simple redefine sclk to a different pin to make the code work.
ARM seems to prefer to change its pin output through IOSET / IOCLR.
To make the existing PICC code work, I would prefer to be able to define certain pins logically, and change their states by referencing their logic names.
how do you do that in ARM? Thanks in advance.
"It looks like you CAN indeed directly reference GPIO ports / bits in a way similar to that used by PIC for some ARM chips and possibly all of them.
For example, LED=~LED where LED is defined as GPIO_PORTA_DATA_R for LM3S628 will flip all bits on PORTA. ARM chips from ADI and ST do allow GPIO direct referrencing - the header files have clear reference to GPIO data bits, control bits, etc."
Did you read my post from 17-Jun-2009 00:14 GMT?
In that post, I already mentioned that a number of ARM processors has a GPIO register that is readable and writeable and where each bit in the register represents one GPIO pin. This allows |=, &= etc to be used on a 8, 16 or 32 bit wide register just as if it was a memory cell.
You will have to load that memory cell into a register, then use any of a large number of possible instructions to update the register, and finally write back the result.
In one post, I also noted that the ARM core does not have instructions to set or clear a bit in a memory cell. Memory writes can only be done on native data types, and the smallest dative data type is a byte, not a bit. But I noted that creating a virtual memory array with one byte/GPIO bit, it is possible to design a chip where it is possible to define a pointer that will update just a single bit. The bit-banding in the Cortex-M3 chips is such a technique.
"now, it does seem that certain manufacturers prefer certain ways to "access" their chips: NXP wants to go through the IO control registers and ADI/ST/Luminary and possibly others want to go through the ports directly, and provide header files to help in the implementation of such approaches, respectively."
Manufacturers mostly tend to prefer access methods that works well with the available instruction set and architecture of the processor core. The instruction set and architecture of the ARM core is different than the PIC core, in which case the manufacturers have looked at other solutions to control GPIO than Microchip has. And I have already mentioned that NXP has chips that allows you to access the port pins directly as if accessing a memory cell.
"Did you read my post from 17-Jun-2009 00:14 GMT?"
so are you going to disagree with your earlier arguments that direct GPIO referencing isn't a) possible / efficient in ARM because the GPIOs hang off a bus; b) possible because ARM's business model doesn't allow that; c) possible because ARM's instruction sets cannot be altered.
or some combination of the above?
no answer required, :).
I did more digging.
looks like TI uses the NXP approach of set and clear to change ports, and Toshiba the PIC approach (through a struct).
the fact that vendors seem to be split on this issue suggests to me that the advantages of setting / clearing are about the same as their disadvantages. or we would have seen a more one-sided outcome.
I know. No answer required, because wheatever I write, you will not be interested in understanding. Probably incapable too.
1) Access to a 8-bit, 16-bit or 32-bit wide PIN register is possible, and was one of the first things I did mention in this thread. Most ARM chips avoids it or suffers significantly because of the big latency involved by the read-modify-write cycles. Especially since older ARM chips had the GPIO one or more bus bridges away. The set and clear registers allows use of the ARM store cache, allowing the core to continue at full speed, as long as the write cache don't gets filled. Hence, quite a number of ARM implementations (different manufactuers have to solve the same problems) have set/clear registers. But I have already mentioned that some ARM chips - including NXP - can have more than just the set/clear registers. And with a direct PIN register together with a mask register, it is possible to avoid the read+modify step and just go for the write step. Already mentioned, but one of the many things you have decided to ignore.
2) The PIC don't just allow byte-wide access to pins, but also allows single-bit access. Possible because the GPIO is memory-mapped into the SFR region inside the core and the PIC has instructions to perform bit operations on that memory - similar to the 8051. So until the Coretex-M3, the ARM chips did not have a way of match the PIC way of direct accessing individual pins. But I did mention that a chip manufacturer could decide themselves if they wanted to use 32 separate memory addresses to allow single-bit writes even if the ARM instruction set and bus can't do bit writes. Just one of the things you decided to ignore.
3) It was you who wondered why the chip manufacturers didn't just modify the core then, in which case I explained that ARM has the license for the instruction set. And ARM sells complete macro cells with the core. So a manufactuer will just have to implement their I/O similar to how you implement peripherial functions around a PC processor. You may integrate in the chipset. Or you may place the peripherial function on a PCI board. Same thing with the ARM. You may connect the GPIO in parallel with AHB bridges. Or after AHB bridges. Or after APB bridges already located after AHB bridges. There is no option but to have the GPIO outside the core. It is then up to design choices and used processes to decide how many steps away from the core the GPIO will be located. With some ARM chips, we may talk about 15 or more wait cycles/access. With some, we may be down to 1 or 2 wait cycles. With full register writes the core can directly overlap the next instruction. But all pins will be affected, unless the processor has a mask register to write-protect some pins. The ARM just happens to be a different architecture than the PIC. Win some. Lose some.
4) You have now multiple times compared chips and specifically mentioned NXP as _not_ allowing pin access, even if I have multiple times mentioned that NXP do have chips supporting it. Yet one more example of your problem reading and picking up facts. Or deciding beforehand what the facts are.
"possible because ARM's business model doesn't allow that" Don't you mean _impossible_? Or is this one of the examples where you are trying to claim I have said something I haven't - possibly something you did say?
"possible because ARM's instruction sets cannot be altered." Same as above.
Per,
Have you considered writing a book? Your posts are often priceless!