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direct referrence to GPIO pins

another newbie question.

I have a piece of code that I am porting from PICC. In PICC, you can make reference to specific pins ("#define sclk GPIO5" for example), and in your code, you can write to sclk to change the pin output on GPOI5. This makes porting code or changing pin layout so much easier as you can simple redefine sclk to a different pin to make the code work.

ARM seems to prefer to change its pin output through IOSET / IOCLR.

To make the existing PICC code work, I would prefer to be able to define certain pins logically, and change their states by referencing their logic names.

how do you do that in ARM? Thanks in advance.

Parents
  • I know. No answer required, because wheatever I write, you will not be interested in understanding. Probably incapable too.

    1) Access to a 8-bit, 16-bit or 32-bit wide PIN register is possible, and was one of the first things I did mention in this thread. Most ARM chips avoids it or suffers significantly because of the big latency involved by the read-modify-write cycles. Especially since older ARM chips had the GPIO one or more bus bridges away. The set and clear registers allows use of the ARM store cache, allowing the core to continue at full speed, as long as the write cache don't gets filled. Hence, quite a number of ARM implementations (different manufactuers have to solve the same problems) have set/clear registers. But I have already mentioned that some ARM chips - including NXP - can have more than just the set/clear registers. And with a direct PIN register together with a mask register, it is possible to avoid the read+modify step and just go for the write step. Already mentioned, but one of the many things you have decided to ignore.

    2) The PIC don't just allow byte-wide access to pins, but also allows single-bit access. Possible because the GPIO is memory-mapped into the SFR region inside the core and the PIC has instructions to perform bit operations on that memory - similar to the 8051. So until the Coretex-M3, the ARM chips did not have a way of match the PIC way of direct accessing individual pins. But I did mention that a chip manufacturer could decide themselves if they wanted to use 32 separate memory addresses to allow single-bit writes even if the ARM instruction set and bus can't do bit writes. Just one of the things you decided to ignore.

    3) It was you who wondered why the chip manufacturers didn't just modify the core then, in which case I explained that ARM has the license for the instruction set. And ARM sells complete macro cells with the core. So a manufactuer will just have to implement their I/O similar to how you implement peripherial functions around a PC processor. You may integrate in the chipset. Or you may place the peripherial function on a PCI board. Same thing with the ARM. You may connect the GPIO in parallel with AHB bridges. Or after AHB bridges. Or after APB bridges already located after AHB bridges. There is no option but to have the GPIO outside the core. It is then up to design choices and used processes to decide how many steps away from the core the GPIO will be located. With some ARM chips, we may talk about 15 or more wait cycles/access. With some, we may be down to 1 or 2 wait cycles. With full register writes the core can directly overlap the next instruction. But all pins will be affected, unless the processor has a mask register to write-protect some pins. The ARM just happens to be a different architecture than the PIC. Win some. Lose some.

    4) You have now multiple times compared chips and specifically mentioned NXP as _not_ allowing pin access, even if I have multiple times mentioned that NXP do have chips supporting it. Yet one more example of your problem reading and picking up facts. Or deciding beforehand what the facts are.

    "possible because ARM's business model doesn't allow that"
    Don't you mean _impossible_? Or is this one of the examples where you are trying to claim I have said something I haven't - possibly something you did say?

    "possible because ARM's instruction sets cannot be altered."
    Same as above.

Reply
  • I know. No answer required, because wheatever I write, you will not be interested in understanding. Probably incapable too.

    1) Access to a 8-bit, 16-bit or 32-bit wide PIN register is possible, and was one of the first things I did mention in this thread. Most ARM chips avoids it or suffers significantly because of the big latency involved by the read-modify-write cycles. Especially since older ARM chips had the GPIO one or more bus bridges away. The set and clear registers allows use of the ARM store cache, allowing the core to continue at full speed, as long as the write cache don't gets filled. Hence, quite a number of ARM implementations (different manufactuers have to solve the same problems) have set/clear registers. But I have already mentioned that some ARM chips - including NXP - can have more than just the set/clear registers. And with a direct PIN register together with a mask register, it is possible to avoid the read+modify step and just go for the write step. Already mentioned, but one of the many things you have decided to ignore.

    2) The PIC don't just allow byte-wide access to pins, but also allows single-bit access. Possible because the GPIO is memory-mapped into the SFR region inside the core and the PIC has instructions to perform bit operations on that memory - similar to the 8051. So until the Coretex-M3, the ARM chips did not have a way of match the PIC way of direct accessing individual pins. But I did mention that a chip manufacturer could decide themselves if they wanted to use 32 separate memory addresses to allow single-bit writes even if the ARM instruction set and bus can't do bit writes. Just one of the things you decided to ignore.

    3) It was you who wondered why the chip manufacturers didn't just modify the core then, in which case I explained that ARM has the license for the instruction set. And ARM sells complete macro cells with the core. So a manufactuer will just have to implement their I/O similar to how you implement peripherial functions around a PC processor. You may integrate in the chipset. Or you may place the peripherial function on a PCI board. Same thing with the ARM. You may connect the GPIO in parallel with AHB bridges. Or after AHB bridges. Or after APB bridges already located after AHB bridges. There is no option but to have the GPIO outside the core. It is then up to design choices and used processes to decide how many steps away from the core the GPIO will be located. With some ARM chips, we may talk about 15 or more wait cycles/access. With some, we may be down to 1 or 2 wait cycles. With full register writes the core can directly overlap the next instruction. But all pins will be affected, unless the processor has a mask register to write-protect some pins. The ARM just happens to be a different architecture than the PIC. Win some. Lose some.

    4) You have now multiple times compared chips and specifically mentioned NXP as _not_ allowing pin access, even if I have multiple times mentioned that NXP do have chips supporting it. Yet one more example of your problem reading and picking up facts. Or deciding beforehand what the facts are.

    "possible because ARM's business model doesn't allow that"
    Don't you mean _impossible_? Or is this one of the examples where you are trying to claim I have said something I haven't - possibly something you did say?

    "possible because ARM's instruction sets cannot be altered."
    Same as above.

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